VERSA: A Tool for the Specification and Analysis of Resource-Bound Real-Time Systems

VERSA is a tool that assists in the algebraic analysis of real-time systems. It is based on ACSR, a timed process algebra designed to express resource-bound real-time distributed systems. VERSA supports the analysis of real-time processes through algebraic rewriting, interactive execution, and equivalence testing. This paper begins by presenting a brief overview of the process algebra ACSR, its syntax, operational semantics, and equivalence relations. VERSA\u27S process and command syntax, its algebraic rewrite system, and its state-based analysis features are described fully. The presentation includes examples that illustrate the salient features of ACSR, and output from sample VERSA sessions that demonstrate the application of the tool to real-time systems analysis

Testing the Electronic Throttle Control

In this report, we summarize our approach for testing the Electronic Throttle Control (ETC) system. We reformulate the ETC model based on the MATLAB/SIMULINK model provided by the Berkeley group. We specify the ETC model using the hybrid modeling language called CHARON. From the CHARON model, we generate test sequences based on the control-flow and data-flow criteria. These are transformed into test cases which may be used to test an implementation of the ETC system

Autophagy protein NRBF2 has reduced expression in Alzheimer\u27s brains and modulates memory and amyloid-beta homeostasis in mice

Background Dysfunctional autophagy is implicated in Alzheimer\u27s Disease (AD) pathogenesis. The alterations in the expression of many autophagy related genes (ATGs) have been reported in AD brains; however, the disparity of the changes confounds the role of autophagy in AD. Methods To further understand the autophagy alteration in AD brains, we analyzed transcriptomic (RNAseq) datasets of several brain regions (BA10, BA22, BA36 and BA44 in 223 patients compared to 59 healthy controls) and measured the expression of 130 ATGs. We used autophagy-deficient mouse models to assess the impact of the identified ATGs depletion on memory, autophagic activity and amyloid-beta (A beta) production. Results We observed significant downregulation of multiple components of two autophagy kinase complexes BECN1-PIK3C3 and ULK1/2-FIP200 specifically in the parahippocampal gyrus (BA36). Most importantly, we demonstrated that deletion of NRBF2, a component of the BECN1-PIK3C3 complex, which also associates with ULK1/2-FIP200 complex, impairs memory in mice, alters long-term potentiation (LTP), reduces autophagy in mouse hippocampus, and promotes A beta accumulation. Furthermore, AAV-mediated NRBF2 overexpression in the hippocampus not only rescues the impaired autophagy and memory deficits in NRBF2-depleted mice, but also reduces beta-amyloid levels and improves memory in an AD mouse model. Conclusions Our data not only implicates NRBF2 deficiency as a risk factor for cognitive impairment associated with AD, but also support the idea of NRBF2 as a potential therapeutic target for AD

Automatic Test Generation from Statecharts Using Model Checking

Abstract This paper discusses the application of model checking to test generation from statecharts. We consider a family of coverage criteria based on the control flow and data flow of statecharts and formulate the problem of test generation as finding counterexamples during the model checking of statecharts. The ability of model checkers to construct counterexamples allows test generation to be automatic. To illustrate our approach, we use the temporal logic CTL and its symbolic model checker SMV. We describe how to translate statecharts to inputs to SMV after defining the semantics of statecharts in terms of Kripke structures. We, then, describe how to express various coverage criteria in CTL and show how SMV can be used to generate only executable tests. 1 Introduction This paper addresses the problem of test generation from statecharts [12] that have been widely used for specifying reactive systems. Statecharts can be regarded as extended finite state machines (EFSM) that support the hierarchical and concurrent structure on states and the communication mechanism through event broadcasting. Among several variants of statecharts considered in the literature [2], we concentrate on the STATEMATE semantics for statecharts [13]. Our approach, however, can be immediately applied to other variants of statecharts semantics, for example, the UML statecharts [24]. A statechart specification typically allows an infinite number of executions and hence exhaustive testing is impossible, which requires all the possible executions be performed. The common testing practice is to construct a test suite, that is, a finite set of test sequences according to certain coverage criteria. For test coverage, we adapt the notions of control flow and data flow coverage used traditionally in software and protocol testing to statecharts. For test generation, we illustrate our approach using the temporal logic CTL [8] and its symbolic model checker SMV [21] to statecharts

Abstract Slicing: A New Approach to Program Slicing Based on Abstract Interpretation and Model Checking

This paper proposes a new approach to program slicing based on abstract interpretation and model checking. First, the notion of abstract slicing is introduced. Abstract slicing extends static slicing with predicates and constraints by using as the program model an abstract state graph, which is obtained by applying predicate abstraction to a program, rather than a flow graph. This leads to a program slice that is more precise and smaller than its static counterpart. Second, a method for performing abstract slicing is developed. It is shown that abstract slicing can be reduced to a least fixpoint computation over formulas in the branching time temporal logic CTL. This enables one to use symbolic model checkers for CTL as an efficient computation engine for abstract slicing. A prototype implementation and experimental results are reported demonstrating the feasibility of the approach

VERSA: A Tool for the Specification and Analysis of Resource-Bound Real-Time Systems

VERSA is a tool that assists in the algebraic analysis of real-time systems. It is based on ACSR, a timed process algebra designed to express resource-bound real-time distributed systems. VERSA is designed to be both a usable and useful tool for the analysis of ACSR specifications. Usability is assured by a flexible user interface that uses ACSR's traditional notation augmented with conventions from programming languages and mathematics that allow concise specification of realistic systems. Usefulness is the result of the breadth of analysis techniques planned and currently implemented, including algebraic term rewriting and state-space exploration based techniques. 1 Introduction Reliability in real-time systems can be improved through the use of formal methods for the specification and analysis of real-time systems. Formal methods treat system components as mathematical objects and provide mathematical models to describe and predict the observable properties and behaviors of..

The Specification and Schedulability Analysis of Real-Time Systems using ACSR

To engineer reliable real-time systems, it is desirable to detect timing anomalies early in the development process. However, there is little work addressing the problem of accurately predicting timing properties of real-time systems before implementations are developed. This paper describes an approach to the specification and schedulability analysis of real-time systems based on the timed process algebra ACSR-VP, which is an extension of ACSR with value-passing communication and dynamic priorities. Combined with the existing features of ACSR for representing time, synchronization and resource requirements, ACSR-VP is capable of specifying a variety of real-time systems with different scheduling disciplines in a modular fashion. Moreover, we can perform schedulability analysis on real-time systems specified in ACSR-VP automatically by checking for a certain bisimulation relation. 1 Introduction As computers become ubiquitous, they are increasingly used in safety critical environment..