Doing Pre-operative Investigations in Emergency Department; a Clinical Audit

Introduction: Pre-operative investigations for emergency surgical patients differ between centers. Following established guidelines can reduce unnecessary investigation, cost of treatment and hospital stay. The present audit was carried out to evaluate the condition of doing pre-operative investigations for three common surgical emergencies compared to National Institute for Health and Care Excellence (NICE) guidelines and local criteria.Methods: A retrospective clinical audit of acute-appendicitis, abscess and hernia patients admitted to the emergency department was carried out over a one-year period from July 2014 to July 2015. Data of laboratory investigations, their indication, cost and duration of hospital stay was collected and compared with NICE-guidelines.Results: A total of 201 patients were admitted to the emergency department during the audit period. These included 77(38.3%) cases of acute-appendicitis, 112 (55.7%) cases of abscesses, and 12 (6%) cases of hernia. Investigations not indicated by NICE-guidelines included 42 (20.9%) full blood counts, 29 (14.4%) random blood sugars, 26 (12.9%) urea tests, 4 (2%) chest x-rays, 13 (6.5%) electrocardiographs, and 58 (28.9%) urine analyses. These cost 25,675 Rupees (245.46 Dollars) in unnecessary investigation costs and 65.7 days of additional hospital stay.Conclusions: Unnecessary investigations for emergency surgical patients can be reduced by following NICE-guidelines. This will reduce workload on emergency services, treatment costs and the length of hospital stay

Health monitoring in proactive reliability management of deteriorating concrete bridges

EThOS - Electronic Theses Online ServiceGBUnited Kingdo

From MARTE to dynamically reconfigurable FPGAs : Introduction of a control extension in a model based design flow

System-on-Chip (SoC) can be considered as a particular case of embedded systems and has rapidly became a de-facto solution for implement- ing these complex systems. However, due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless method- ologies and tools to handle the SoC co-design aspects. This paper addresses this issue and proposes a novel SoC co-design methodology based on Model Driven Engineering (MDE) and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by OMG (Object Management Group), in order to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs; and allow to implement the notion of Partial Dy- namic Reconfiguration supported by current FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in UML (Unified Modeling Language); and afterwards, transform these high level mod- els into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis

MARTE based design approach for targeting Reconfigurable Architectures

International audienceThis paper demonstrates the use of a model driven design flow for Multiprocessor System on chips (MPSoCs) such as those dedicated to intensive signal processing applications. Due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. This paper addresses this issue and proposes a novel SoC codesign methodology based on Model Driven Engineering (MDE) and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by OMG (Object Management Group), in order to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs

Tutorial: Using the UML profile for MARTE to MPSoC co-design dedicated to signal processing

International audienceThis paper demonstrates the use of a model driven design flow for Multiprocessor System on chips (MPSoCs) such as those dedicated to intensive signal processing applications. The most intensive part of these applications is usually composed of systematic signal processing followed by intensive data processing. The systematic signal processing mainly consists of a chain of filters and regular processing applied on the input signals independently of the signal values. It results in a characterization of the input signals with values of interest. The intensive data processing applies irregular computations on these values of interest. Those computations may depend on the signal values. Examples of these applications are Software Radio Receiver, Sonar Beam Forming and Multimedia video codes

Modeling of Topologies of Interconnection Networks based on Multidimensional Multiplicity

Modern SoCs are becoming more complex with the integration of heterogeneous components (IPs). For this purpose, a high performance interconnection medium is required to handle the complexity. Hence NoCs come into play enabling the integration of more IPs into the SoC with increased performance. These NoCs are based on the concept of Interconnection networks used to connect parallel machines. In response to the MARTE RFP of the OMG, a notation of multidimensional multiplicity has been proposed which permits to model repetitive structures and topologies. This report presents a modeling methodology based on this notation that can be used to model a family of Interconnection Networks called Delta Networks which in turn can be used for the construction of NoCs

High level modeling of Partially Dynamically Reconfigurable FPGAs based on MDE and MARTE

International audienceSystem-on-Chip (SoC) architectures are becoming the preferred solution for implementing modern embedded systems. However their design complexity continues to augment due to the increase in integrated hardware resources requiring new design methodologies and tools. In this paper we present a novel SoC co-design methodology based on aModel Driven Engineering framework while utilizing the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology permits us to model fine grain reconfigurable architectures such as FPGAs and allows to extend the standard for integrating new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The overall objective is to carry out modeling at a high abstraction level expressed in a graphical language like UML (Unified Modeling Language) and afterwards transformations of these models, automatically generate the necessary specifications required for FPGA implementation