The Chinese Navy\u27s Offshore Active Defense Strategy

On 25 February 1992, the National People\u27s Congress, China\u27s nominal legislative body, passed the Law of the Territorial Sea and Contiguous Zone and formally legalized the People\u27s Republic of China\u27s maritime territorial claims.1 Article 2 of the Law listed a number of unsettled archipelagos in the western Pacific as China\u27s inherited maritime territories.2 Three months later, the PRC announced that it had signed a joint contract with the Crestone Energy Corporation of the United States for oil exploration in an offshore block contiguous to a Vietnamese oil field

The PLA over the China Seas and Maritime Sovereignty Dispute

[[conferencetype]]國際[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]Virginia, US

A Dynamic Model of Decision-making in the IS/IT Outsourcing Process: A Case Study from a Government-supported

The IS/IT outsourcing process is complex and the outcome is unpredictable, especially in the varied participants, complicated social and political environments. Prior research on IS/IT outsourcing decisions simply assumed the rational, comprehensive, independent decisionmaking activity is not descriptively accurate and perhaps thus cannot be prescriptively useful in this complex environment. To get deeper understandings of the decision-making in the IS/IT outsourcing process, this research creates a dynamic model to illustrate the complex phenomenon. In-depth case study methodology and process-oriented analysis strategy were used to interpret a government-supported, outsourced IS project. This study indicates that decision makers should regard the IS/IT outsourcing process as a continuous, integral process in context and consider the structural influence, antecedent conditions, and future impact in every decision episode. This paper provides an initial insight by studying IS/IT outsourcing decision-making through dynamic and process perspective

Unpacking the Network Pictures of the ICT industry in Taiwan

This study analyzes how a developmental state fosters its ICT industries through the network alliances among a boundary organization and ICT industries. The cooperative networks of ICT industries play a strategic role for the national development in a global networked economy. We argue that different network pictures lead to different managerial strategies and capabilities. Drawing on studies of network pictures, this study details an interpretive case study in a major semi-government sponsored ICT marketing research institute in Taiwan. We explore the relationships between this boundary organization, ICT businesses and their dynamic networking relationship. The findings highlight how the inertia of network pictures stabilizes value creation activities and capabilities in the boundary organization, thus limiting it opening to a more radical future-oriented strategic network

COLLABORATIVE AND EMBEDDED：KNOWLEDGE BOUNDARIES OF AN ICT CONSULTING FIRM

Knowledge is not embedded in organizations’ boundaries but their collaborative networks cross organizations. The paper indicates knowledge boundaries are formed by their respective social contexts, relationships and practices of networks through participative observing two practice teams of an ICT consulting firm.To emphasis, the teams’ perspectives, knowledge structures, knowledge values, identities, teamwork styles are affected by their knowledge boundaries.The implication of knowledge boundaries on key topics in teams’ knowledge governance, professional service firms’ market entering strategies, and national knowledge innovation issues are discussed.This research provides a new direction to take industry seriously in the knowledge management of IS research

The Mediating Effect of Commitment on Customer Loyalty in eBrokerage: An Enhanced Investment Model

Customers could switch service provider easily because of lower searching cost and identical service in online environment. Most marketing research for customer loyalty emphasizes the effect of satisfaction and switching barrier, derived from investment model. However, how satisfaction and switching barrier influence customer loyalty has been less conclusive. The possible reason is neglect of commitment. We inject the concept of commitment in relationship marketing, which consists of affective and continuous commitment, into investment model for enhancing mediating role of commitment. Empirical results gathered from online survey in virtual financial communities show that commitment is the essential mediator in cultivating customer loyalty. Besides, satisfaction and switching barrier influence loyalty by different component of commitment, affective continuous commitment respectively. Affective commitment is more important than continuous commitment. E-brokerage should pay attention to earning customers’ commitment for retaining customers

Optimizing cache utilization in modern cache hierarchies

Memory wall is one of the major performance bottlenecks in modern computer systems. SRAM caches have been used to successfully bridge the performance gap between the processor and the memory. However, SRAM cache’s latency is inversely proportional to its size. Therefore, simply increasing the size of caches could result in negative impact on performance. To solve this problem, modern processors employ multiple levels of caches, each of a different size, forming the so called memory hierarchy. Upon a miss, the processor will start to lookup the data from the highest level (L1 cache) to the lowest level (main memory). Such a design can effectively reduce the negative performance impact of simply using a large cache. However, because SRAM has lower storage density compared to other volatile storage, the size of an SRAM cache is restricted by the available on-chip area. With modern applications requiring more and more memory, researchers are continuing to look at techniques for increasing the effective cache capacity. In general, researchers are approaching this problem from two angles: maximizing the utilization of current SRAM caches or exploiting new technology to support larger capacity in cache hierarchies. The first part of this thesis focuses on how to maximize the utilization of existing SRAM cache. In our first work, we observe that not all words belonging to a cache block are accessed around the same time. In fact, a subset of words are consistently accessed sooner than others. We call this subset of words as critical words. In our study, we found these critical words can be predicted by using access footprint. Based on this observation, we propose critical-words-only cache (co cache). Unlike the conventional cache which stores all words that belongs to a block, co-cache only stores the words that we predict as critical. In this work, we convert an L2 cache to a co-cache and use L1s access footprint information to predict critical words. Our experiments show the co-cache can outperform a conventional L2 cache in the workloads whose working-set-sizes are greater than the L2 cache size. To handle the workloads whose working-set-sizes fit in the conventional L2, we propose the adaptive co-cache (acocache) which allows the co-cache to be configured back to the conventional cache. The second part of this thesis focuses on how to efficiently enable a large capacity on-chip cache. In the near future, 3D stacking technology will allow us to stack one or multiple DRAM chip(s) onto the processor. The total size of these chips is expected to be on the order of hundreds of megabytes or even few gigabytes. Recent works have proposed to use this space as an on-chip DRAM cache. However, the tags of the DRAM cache have created a classic space/time trade-off issue. On the one hand, we would like the latency of a tag access to be small as it would contribute to both hit and miss latencies. Accordingly, we would like to store these tags in a faster media such as SRAM. However, with hundreds of megabytes of die-stacked DRAM cache, the space overhead of the tags would be huge. For example, it would cost around 12 MB of SRAM space to store all the tags of a 256MB DRAM cache (if we used conventional 64B blocks). Clearly this is too large, considering that some of the current chip multiprocessors have an L3 that is smaller. Prior works have proposed to store these tags along with the data in the stacked DRAM array (tags-in-DRAM). However, this scheme increases the access latency of the DRAM cache. To optimize access latency in the DRAM cache, we propose aggressive tag cache (ATCache). Similar to a conventional cache, the ATCache caches recently accessed tags to exploit temporal locality; it exploits spatial locality by prefetching tags from nearby cache sets. In addition, we also address the high miss latency issue and cache pollution caused by excessive prefetching. To reduce this overhead, we propose a cost-effective prefetching, which is a combination of dynamic prefetching granularity tunning and hit-prefetching, to throttle the number of sets prefetched. Our proposed ATCache (which consumes 0.4% of overall tag size) can satisfy over 60% of DRAM cache tag accesses on average. The last proposed work in this thesis is a DRAM-Cache-Aware (DCA) DRAM controller. In this work, we first address the challenge of scheduling requests in the DRAM cache. While many recent DRAM works have built their techniques based on a tagsin- DRAM scheme, storing these tags in the DRAM array, however, increases the complexity of a DRAM cache request. In contrast to a conventional request to DRAM main memory, a request to the DRAM cache will now translate into multiple DRAM cache accesses (tag and data). In this work, we address challenges of how to schedule these DRAM cache accesses. We start by exploring whether or not a conventional DRAM controller will work well in this scenario. We introduce two potential designs and study their limitations. From this study, we derive a set of design principles that an ideal DRAM cache controller must satisfy. We then propose a DRAM-cache-aware (DCA) DRAM controller that is based on these design principles. Our experimental results show that DCA can outperform the baseline over 14%

Nanographite/polyaniline composite films as the counter electrodes for dye-sensitized solar cells

100學年度研究獎補助論文[[abstract]]Nanographite/polyaniline (NG/PANI) composite films were developed and characterized, and the performances of the dye-sensitized solar cells (DSSCs) employing these composite films as the counter electrode (CE) were evaluated in this study. The nanographite/aniline (NG/ANI) particle was firstly synthesized by a reflux method and served as the monomer for the electro-polymerization of the NG/PANI composite films. The surface modification of NG by ANI was confirmed by EDX mapping, TEM image, zeta-potential, and UV-Vis absorption measurements. The electro-polymerized NG/PANI composite films were characterized by Raman spectroscopy, XPS, and conducting-AFM, which verified the successful incorporation of NGs in the PANI films. The electro-catalytic activity of the NG/PANI composite film was evaluated using the positive-feedback mode of scanning electrochemical microscopy (SECM), by which a comparable heterogeneous rate constant (ks0) for the ferrocene/ferrocenium (Fc/Fc+) redox pair was obtained and compared with that of a sputtered Pt. The DSSC employing the NG/PANI (20 mC cm−2) CE exhibited a higher short-circuit current density (JSC) but lower fill factor (FF), and gave a comparable power-conversion efficiency (η) of 7.07%, as compared to that of a DSSC containing a sputtered Pt CE (η = 7.19%).[[incitationindex]]SCI[[booktype]]紙