Characterization of Electrically Active Defects in Advanced Gate Dielectrics

As the gate oxide thickness of the metal-oxide-semiconductor (MOS) Field Effect Transistor (FET) is continuously scaled down with lateral device dimensions, the gate leakage current during operation increases exponentially. This increase in leakage current raises concerns regarding device reliability. Substitute dielectrics with high dielectric constant (high-k) have been proposed to replace traditional SiO2 to reduce the leakage current in future devices. However, these high-k dielectrics also have reliability issues due to the large amount of intrinsic trapping centers. In this work, electrically active defects generated during electrical stress of ultrathin SiO2 dielectrics are characterized and studied. The mechanism of oxide breakdown is studied by investigating the contributions of hot holes to device time-to-breakdown (tbd). The proper extrapolation of tbd from accelerated testing conditions to normal device operating conditions is also studied. The factors that affect this extrapolation are discussed. Another important device reliability parameter, threshold voltage shift (Vth), is also investigated in this work. The dominant mechanisms causing this shift is studied using both simulation and experimental results. The current primary reliability issue with high-k dielectrics is the large amount of intrinsic traps located in the dielectric stack. Therefore, the electrical characterization of high-k dielectrics in this work is focused on these initial as-fabricated trapping centers. A methodology based on 2-level charge pumping (CP) measurements at different frequencies is used to study the spatial profile of these trapping centers. The correlation between device fabrication data and measurement results indicates this methodology is accurate and reliable

Total Ionization Radiation Sensor Performance Improvement by Using Si-rich MONOS Device

The Si-rich metal -oxide-nitride-oxide-silicon (hereafter Si-MONOS) can be candidates for non-volatile total ionization dose (TID) radiation sensors. In the case of Si-MONOS gamma radiation sensors, the gamma radiation induces a significant decrease of threshold voltage VT. The change of VT for Si-MONOS after gamma irradiation has a strong correlation to the TID of gamma ray exposure as well. The Si-MONOS capacitor device in this study has demonstrated the better feasibility for non-volatile TID radiation sensing in the future

Public Value:Deepening, Enriching and Broadening Theory and Practice

Test structures for accurate UHF capacitance –voltage (C-V) measurements of high performance CMOSFETs with Hf-based high-k dielectric and TiN metal gate are analyzed. It is shown that series resistance or substrate resistance between the channel region and body contact plays a role in UHF C-V measurements. The substrate resistance beneath the gate region also impacts accurate UHF C-V measurements. Therefore, minimization of series resistance through short gate lengths with a minimum distance between the source/drain and body contact is highly desired for an accurate evaluation of gate dielectric thickness using UHF C-V measurements

Improved Ge surface passivation with ultrathin SiO/sub x/ enabling high-mobility surface channel pMOSFETs featuring a HfSiO/WN gate stack

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiOX passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm2 • V−1 • s−1 at 0.05 MV/cm—a 2× enhancement over the universal Si/SiO2 mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an ION/IOFF ratio of 3 × 103 without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface

Improved Ge surface passivation with ultrathin SiO/sub x/ enabling high-mobility surface channel pMOSFETs featuring a HfSiO/WN gate stack

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiOX passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm2 • V−1 • s−1 at 0.05 MV/cm—a 2× enhancement over the universal Si/SiO2 mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an ION/IOFF ratio of 3 × 103 without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface

High <i>K</i> Nanophase Zinc Oxide on Biomimetic Silicon Nanotip Array as Supercapacitors

A 3D trenched-structure metal–insulator–metal (MIM) nanocapacitor array with an ultrahigh equivalent planar capacitance (EPC) of ∼300 μF cm^–2 is demonstrated. Zinc oxide (ZnO) and aluminum oxide (Al₂O₃) bilayer dielectric is deposited on 1 μm high biomimetic silicon nanotip (SiNT) substrate using the atomic layer deposition method. The large EPC is achieved by utilizing the large surface area of the densely packed SiNT (∼5 × 10¹⁰ cm^–2) coated conformally with an ultrahigh dielectric constant of ZnO. The EPC value is 30 times higher than those previously reported in metal–insulator–metal or metal–insulator–semiconductor nanocapacitors using similar porosity dimensions of the support materials