A general model for EV drivers' charging behavior

The increasing adoption of electric vehicles (EVs) due to technical advancements and environmental concerns requires wide deployment of public charging stations (CSs). In order to accelerate the EV penetration and predict the future CSs requirements and adopt proper policies for their deployment, studying the charging behavior of EV drivers is inevitable. This paper introduces a stochastic model that takes into consideration the behavioral characteristics of EV drivers in particular, in terms of their reaction to the EV battery charge level when deciding to charge or disconnect at a CS. The proposed model is applied in two case studies to describe the resultant collective behavior of EV drivers in a community using real field EV data obtained from a major North American campus network and part of London urban area. The model fits well to the datasets by tuning the model parameters. The sensitivity analysis of the model indicates that changes in the behavioral parameters affect the statistical characteristics of charging duration, vehicle connection time, and EV demand profile, which has a substantial effect on congestion status in CSs. This proposed model is then applied in several scenarios to simulate the congestion status in public parking lots and predict the future charging points needed to guarantee the appropriate level of service quality. The results show that studying and controlling the EV drivers’ behavior leads to a significant saving in CS capacity and results in consumer satisfaction, thus, profitability of the station owners

Peer-assisted Information-Centric Network (PICN): A Backward Compatible Solution

International audienceInformation-Centric Networking (ICN) is a promising solution for most of Internet applications where the content represents the core of the application. However, the proposed solutions for the ICN architecture are associated with many complexities including pervasive caching in the Internet and incompatibility with legacy IP networks, so the deployment of ICN in real networks is still an open problem. In this paper, we propose a backward compatible ICN architecture to address the caching issue in particular. The key idea is implementing edge caching in ICN, using a coalition of end clients and edge servers. Our solution can be deployed in IP networks with HTTP requests. We performed a trace-driven simulation for analyzing PICN benefits using IRCache and Berkeley trace files. The results show that in average, PICN decreases the latency for 78% and increases the content retrieval speed for 69% compared to a direct download from the original web servers. When comparing PICN with a solution based on central proxy servers, we show that the hit ratio obtained using a small cache size in each PICN client is almost 14% higher than the hit ratio obtained with a central proxy server using an unlimited cache storage

Scheduling engines for ATM switches

grantor: University of TorontoBroadband integrated services networks should support a wide range of services with different quality of service requirements. Guaranteed quality of service is a major goal of ATM networks as the prime candidate for broadband networks. Queue scheduling in ATM switches plays a fundamental role in providing the quality of service for connections. Several scheduling algorithms have been proposed for ATM switches, but until recently only a few of these schemes have been adapted for implementation in the switches, mostly because of hardware complexity and difficulty of incorporating the scheduling with switching. This dissertation is on the design of flexible hardware engines for implementation of scheduling schemes in ATM switches. We first introduce and describe a generalized sequencer which is capable of sorting ATM cells into a queue according to a tag attached to each cell. The logic of sorting can be designed flexibly to achieve any logical arrangement of the cells. We show that by appropriate design of the sorting logic and the tag of cells, a wide range of scheduling algorithms can be implemented. A programmable scheduler can also be designed using the generalized sequencer architecture. Next we introduce a new approach to ATM switching by presenting the single-queue switch architecture. In this architecture we use the capabilities of the generalized sequencer architecture to build a switch out of the sequencer by interleaving the (logical) output queues of the switch into a single sequencer. In this way the difficult task of combining output queueing and full buffer sharing is achieved easily. Queue scheduling in each logical output queue can be done similar to the sequencer. A bank of sequencers, or in its compact form a single-queue switch can be used as the queue controller in RAM-based shared-memory switch to benefit from the advantages of both the RAM-based architecture and sequencer or single-queue circuit. In both cases multicasting can also be incorporated. We introduce a multicasting version of the single-queue switch with a novel copy mechanism which requires no extra buffering space for copied cells, and can provide priority control between multicast cells as well as between multicast cells and the head-of-line cell in contending unicast queues. Next we introduce a version of the single-queue switch which in conjunction with a low-speed RAM, both operating in line speed, can provide separate (logical) output queues for each output line at each input of the switch to eliminate the HoL blocking problem which is the major drawback of input-buffered ATM switches. The switch provides scheduling within each queue as before. Finally, we present the design of a generic packet switch which can handle variable-length packets based on different networking protocols including IP and ATM. In this design we use the generalized sequencer and the single-queue switch circuits to schedule variable-length packets.Ph.D