Event-based processing of single photon avalanche diode sensors

Single Photon Avalanche Diode sensor arrays operating in direct time of flight mode can perform 3D imaging using pulsed lasers. Operating at high frame rates, SPAD imagers typically generate large volumes of noisy and largely redundant spatio-temporal data. This results in communication bottlenecks and unnecessary data processing. In this work, we propose a neuromorphic processing solution to this problem. By processing the spatio-temporal patterns generated by the SPADs in a local, event-based manner, the proposed 128 imes 128 pixel sensor-processor system reduces the size of output data from the sensor by orders of magnitude while increasing the utility of the output data in the context of challenging recognition tasks. To test the proposed system, the first large scale complex SPAD imaging dataset is captured using an existing 32 imes 32 pixel sensor. The generated dataset consists of 24000 recordings and involves high-speed view-invariant recognition of airplanes with background clutter. The frame-based SPAD imaging dataset is converted via several alternative methods into event-based data streams and processed using the proposed 125 imes 125 receptive field neuromorphic processor as well as a range of feature extractor networks and pooling methods. The output of the proposed event generation methods are then processed by an event-based feature extraction and classification system implemented in FPGA hardware. The event-based processing methods are compared to processing the original frame-based dataset via frame-based but otherwise identical architectures. The results show the event-based methods are superior to the frame-based approach both in terms of classification accuracy and output data-rate

Post-peak fracture behavior during direct shear tests of rock joints

see Abstract Volum

A simple sequent calculus for nominal logic

The front end of the human auditory system, the cochlea, converts sound signals from the outside world into neural impulses transmitted along the auditory pathway for further processing. The cochlea senses and separates sound in a nonlinear active fashion, exhibiting remarkable sensitivity and frequency discrimination. Although several electronic models of the cochlea have been proposed and implemented, none of these are able to reproduce all the characteristics of the cochlea, including large dynamic range, large gain and sharp tuning at low sound levels, and low gain and broad tuning at intense sound levels. Here, we implement the 'Cascade of Asymmetric Resonators' (CAR) model of the cochlea on an FPGA. CAR represents the basilar membrane filter in the 'Cascade of Asymmetric Resonators with Fast-Acting Compression' (CAR-FAC) cochlear model. CAR-FAC is a neuromorphic model of hearing based on a pole-zero filter cascade model of auditory filtering. It uses simple nonlinear extensions of conventional digital filter stages that are well suited to FPGA implementations, so that we are able to implement up to 1224 cochlear sections on Virtex-6 FPGA to process sound data in real time. The FPGA implementation of the electronic cochlea described here may be used as a front-end sound analyser for various machine-hearing applications

A low power neural recording amplifier with programmable gain and bandwidth

In this paper we present the design and implementation of a low power neural amplifer which has two programmable gains in two programmable bandwidths. The bandwidths are programmable between 0.7–300Hz, suitable for measuring local field potentials and 1.95–5.4kHz, suitable for measuring action potentials. The amplifier achieves a maximum gain of 79dB in the higher bandwidth. A chip has been designed and implemented using a 0.5_m technology with 8 neural amplifiers. On average the neural amplifier consumes less than 14_W at 3.3V

A synchronous buck-boost converter on a Silicon-on-Sapphire 0.5µm process

This paper presents the design of a synchronous non-inverting buck-boost DC-DC converter on a Silicon-on-Sapphire (SOS) 0.5μm process. The converter uses voltage-mode feedback and PWM control to regulate the power delivered to a range of output voltages and loads. The circuit has been simulated using Cadence and its performance has been measured. The converter has an output voltage range of 1.2-4V and can deliver up to 750 mA. It is up to 92% efficient with a maximum ripple voltage of 80mV and uses significantly less die area than similar converters on standard CMOS processes

A reconfigurable buck-boost switched capacitor converter architecture for multiple, distributed on-chip load applications

This paper presents the design of a dual-output reconfigurable buck-boost switched capacitor converter architecture that can be adapted for applications requiring multiple, distributed on-chip loads. This system uses adaptive gain control and discrete frequency scaling to regulate power delivered. Core-interleaving and an enhanced load regulation scheme have also been adopted to improve performance. The converter provides a fully-integrated, low-area and fully digital solution. Design and implementation using a standard bulk CMOS 0.18μm process provide simulation results showing that the converter has an output voltage range of 1.0-2.2V, can deliver up to 5mA in load current and is up to 67% efficient

A neuromorphic cross-correlation chip

The cross-correlation and auto-correlation operations are important in many signal processing tasks. Often these operations are resource intensive or limited by noise in low-power systems. In this paper we present the design and measured results of an analogue integrated circuit (IC) that performs cross-correlations using a neuromorphic algorithm

Silicon cochlea building blocks

This chapter goes into the details of some of the circuit blocks used in the silicon cochleas discussed in Chapter 4. It looks at some of the basic circuit structures used in the design of various one-dimensional (1D) and two-dimensional (2D) silicon cochleas. Nearly all silicon cochleas are built around second-order low-pass or band-pass filters. These filters are usually described as second-order sections

A reconfigurable dual-output buck-boost switched-capacitor converter using adaptive gain and discrete frequency scaling control

This paper presents the design of a dual-output reconfigurable buck-boost switched capacitor converter architecture that can be adapted for applications requiring multiple, distributed on-chip loads. This system uses adaptive gain control and discrete frequency scaling to regulate power delivered. Core-interleaving, an enhanced load regulation scheme, and adaptive switch-sizing control have also been adopted to improve performance. The converter provides a fully-integrated, low-area and fully digital solution. Design and implementation using a standard bulk-CMOS 0.18 µm process provide simulation results showing that the converter has an output voltage range of 1.0–2.2 V, can deliver up to 7.5 mW of power to each load, and is up to 67% efficient, using an active area of only 0.06 mm2

The Synaptic Kernel Adaptation Network

In this paper we present the Synaptic Kernel Adaptation Network (SKAN) circuit, a dynamic circuit that implements Spike Timing Dependent Plasticity (STDP), not by adjusting synaptic weights but via dynamic synaptic kernels. SKAN performs unsupervised learning of the commonest spatio-temporal pattern of input spikes using simple analog or digital circuits. It features tunable robustness to temporal jitter and will unlearn a pattern that has not been present for a period of time using tunable 'forgetting' parameters. It is compact and scalable for use as a building block in a larger network to form a multilayer hierarchical unsupervised memory system which develops models based on the temporal statistics of its environment. Here we show results from simulations as well present digital and analog implementations. Our results show that the SKAN is fast, accurate and robust to noise and jitter