Delay Learning Architectures for Memory and Classification

We present a neuromorphic spiking neural network, the DELTRON, that can remember and store patterns by changing the delays of every connection as opposed to modifying the weights. The advantage of this architecture over traditional weight based ones is simpler hardware implementation without multipliers or digital-analog converters (DACs) as well as being suited to time-based computing. The name is derived due to similarity in the learning rule with an earlier architecture called Tempotron. The DELTRON can remember more patterns than other delay-based networks by modifying a few delays to remember the most 'salient' or synchronous part of every spike pattern. We present simulations of memory capacity and classification ability of the DELTRON for different random spatio-temporal spike patterns. The memory capacity for noisy spike patterns and missing spikes are also shown. Finally, we present SPICE simulation results of the core circuits involved in a reconfigurable mixed signal implementation of this architecture.Comment: 27 pages, 20 figure

Racing to Learn: Statistical Inference and Learning in a Single Spiking Neuron with Adaptive Kernels

This paper describes the Synapto-dendritic Kernel Adapting Neuron (SKAN), a simple spiking neuron model that performs statistical inference and unsupervised learning of spatiotemporal spike patterns. SKAN is the first proposed neuron model to investigate the effects of dynamic synapto-dendritic kernels and demonstrate their computational power even at the single neuron scale. The rule-set defining the neuron is simple there are no complex mathematical operations such as normalization, exponentiation or even multiplication. The functionalities of SKAN emerge from the real-time interaction of simple additive and binary processes. Like a biological neuron, SKAN is robust to signal and parameter noise, and can utilize both in its operations. At the network scale neurons are locked in a race with each other with the fastest neuron to spike effectively hiding its learnt pattern from its neighbors. The robustness to noise, high speed and simple building blocks not only make SKAN an interesting neuron model in computational neuroscience, but also make it ideal for implementation in digital and analog neuromorphic systems which is demonstrated through an implementation in a Field Programmable Gate Array (FPGA).Comment: In submission to Frontiers in Neuroscienc

A compact aVLSI conductance-based silicon neuron

We present an analogue Very Large Scale Integration (aVLSI) implementation that uses first-order lowpass filters to implement a conductance-based silicon neuron for high-speed neuromorphic systems. The aVLSI neuron consists of a soma (cell body) and a single synapse, which is capable of linearly summing both the excitatory and inhibitory postsynaptic potentials (EPSP and IPSP) generated by the spikes arriving from different sources. Rather than biasing the silicon neuron with different parameters for different spiking patterns, as is typically done, we provide digital control signals, generated by an FPGA, to the silicon neuron to obtain different spiking behaviours. The proposed neuron is only ~26.5 um2 in the IBM 130nm process and thus can be integrated at very high density. Circuit simulations show that this neuron can emulate different spiking behaviours observed in biological neurons.Comment: BioCAS-201

A Reconfigurable Mixed-signal Implementation of a Neuromorphic ADC

We present a neuromorphic Analogue-to-Digital Converter (ADC), which uses integrate-and-fire (I&F) neurons as the encoders of the analogue signal, with modulated inhibitions to decohere the neuronal spikes trains. The architecture consists of an analogue chip and a control module. The analogue chip comprises two scan chains and a twodimensional integrate-and-fire neuronal array. Individual neurons are accessed via the chains one by one without any encoder decoder or arbiter. The control module is implemented on an FPGA (Field Programmable Gate Array), which sends scan enable signals to the scan chains and controls the inhibition for individual neurons. Since the control module is implemented on an FPGA, it can be easily reconfigured. Additionally, we propose a pulse width modulation methodology for the lateral inhibition, which makes use of different pulse widths indicating different strengths of inhibition for each individual neuron to decohere neuronal spikes. Software simulations in this paper tested the robustness of the proposed ADC architecture to fixed random noise. A circuit simulation using ten neurons shows the performance and the feasibility of the architecture.Comment: BioCAS-201

Cross-sectional Study of Factors Associated With Suicide Ideation in Ontario Adolescents

Objective: Suicide is the second leading cause of death in Canadian adolescents. The Interpersonal Theory of Suicide attempts to explain suicide etiology and proposes that feelings of perceived burdensomeness or thwarted belongingness lead to suicide ideation, but this has not been extensively studied in adolescents. This study aimed to use the Interpersonal Theory of Suicide to examine factors that may be associated with suicide ideation in adolescents. The factors of interest were school connectedness, perceived availability of support, self-esteem, feelings of worthlessness, feelings of hopelessness, bullying and cyberbullying victimization, substance use, and social media use. Methods: Data were from the 2017 Ontario Student Drug Use and Health Survey, a survey of 7th to 12th graders enrolled in a publicly funded school in Ontario. Weighted multivariate logistic regression of suicide ideation on all exposure variables was conducted. Results: 13.6% of students in the sample endorsed having suicidal ideation in the preceding 12 months. Not knowing where to turn to for support, feeling worthless, endorsing low self-esteem, being bullied, and using cannabis were each associated with greater odds of suicide ideation. Feeling hopeless, social media use, using alcohol and tobacco, and being cyberbullied were not associated with suicide ideation in the weighted multivariate logistic regression model. Conclusions: This study is consistent with the Interpersonal Theory of Suicide as low self-esteem and feelings of worthlessness, two indicators of perceived burdensomeness, and not knowing where to turn to for support, an indicator of thwarted belongingness, were associated with greater odds of suicide ideation. These findings can help guide interventions aimed at reducing the burden of suicidality during adolescence and demonstrate the need to provide accessible mental health support for youth

Symbolic analysis of tau cell log-domain filter using affine MOSFET models

This paper analyses a filter known as the Tau Cell using symbolic methods and shows that the operation of this filter is independent of the magnitude of the input DC offset. This means that the circuit places no restrictions on whether the input DC offset is a sub-threshold current or not. The circuit behaviour predicted from symbolic analysis was observed in similar circuits on a chip fabricated using MOSIS AMI 1.6μm technology. This paper highlights the utility of symbolic analysis and shows that it is a powerful tool for circuit analysis and design

A W-Band SPDT Switch with 15 dBm P1dB in 55-nm Bulk CMOS

© 2022 IEEE -This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/LMWC.2022.3159529Power-handling capability of bulk CMOS-based single-pole double-throw switch operating in millimetre-wave and sub-THz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100 GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss of 3.5 dB and an isolation of 18 dB. The total area of the chip is only 0.14 mm2.Peer reviewe

A 90-GHz Asymmetrical Single-Pole Double-Throw Switch with >19.5-dBm 1-dB Compression Point in Transmission Mode Using 55-nm Bulk CMOS Technology

© Copyright 2021 IEEE. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCSI.2021.3106231The millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm2.Peer reviewe