We present an analogue Very Large Scale Integration (aVLSI) implementation
that uses first-order lowpass filters to implement a conductance-based silicon
neuron for high-speed neuromorphic systems. The aVLSI neuron consists of a soma
(cell body) and a single synapse, which is capable of linearly summing both the
excitatory and inhibitory postsynaptic potentials (EPSP and IPSP) generated by
the spikes arriving from different sources. Rather than biasing the silicon
neuron with different parameters for different spiking patterns, as is
typically done, we provide digital control signals, generated by an FPGA, to
the silicon neuron to obtain different spiking behaviours. The proposed neuron
is only ~26.5 um2 in the IBM 130nm process and thus can be integrated at very
high density. Circuit simulations show that this neuron can emulate different
spiking behaviours observed in biological neurons.Comment: BioCAS-201
