Vector Symbolic Finite State Machines in Attractor Neural Networks

Hopfield attractor networks are robust distributed models of human memory. We propose construction rules such that an attractor network may implement an arbitrary finite state machine (FSM), where states and stimuli are represented by high-dimensional random bipolar vectors, and all state transitions are enacted by the attractor network's dynamics. Numerical simulations show the capacity of the model, in terms of the maximum size of implementable FSM, to be linear in the size of the attractor network. We show that the model is robust to imprecise and noisy weights, and so a prime candidate for implementation with high-density but unreliable devices. By endowing attractor networks with the ability to emulate arbitrary FSMs, we propose a plausible path by which FSMs may exist as a distributed computational primitive in biological neural networks

Synaptic Normalisation for On-Chip Learning in Analog CMOS Spiking Neural Networks

Spiking Neural Networks (SNNs) are becoming increasingly popular for their application in Edge Artificial Intelligence (Edge-AI) due to their sparse and low-latency computation. Among these networks, analog hardware SNNs are chosen for their ability to emulate complex dynamics in neurons and synapses, especially in integrated Metal Oxide Semiconductor (MOS) technology. They can form memories of external stimuli by modulating the strength of synaptic weights. In this context, binary weights are a common hardware design choice, due to their ease to program and store. The use of binary weights in SNNs worsens the bias introduced by the coding level of input stimuli (i.e. fraction of active input nodes), where the network activity is highly correlated to the number of excited neurons. In this paper, we present a Complementary Metal Oxide Semiconductor (CMOS) solution for the coding level bias, by proposing a novel circuit that employs synaptic normalisation at the neuron level. This circuit modifies the gain of the neuron depending on its input weights, with a small footprint and therefore high scalability

Robust Spiking Attractor Networks with a Hard Winner-Take-All Neuron Circuit

Attractor networks are widely understood to be a re-occurring primitive that underlies cognitive function. Stabilising activity in spiking attractor networks however remains a difficult task, especially when implemented in analog integrated circuits (aIC). We introduce here a novel circuit implementation of a hard Winner-Take-All (hWTA) mechanism, in which competing neurons' refractory circuits are coupled together, and thus their spiking is forced to be mutually exclusive. We demonstrate stable persistent-firing attractor dynamics in a small on-chip network consisting of hWTA-connected neurons and excitatory recurrent synapses. Its utility within larger networks is demonstrated in simulation, and shown to support overlapping attractors and be robust to synaptic weight mismatch. The realised hWTA mechanism is thus useful for stabilising activity in spiking networks composed of unreliable components, without the need for careful parameter tuning

Closed-loop sound source localization in neuromorphic systems

Sound source localization (SSL) is used in various applications such as industrial noise-control, speech detection in mobile phones, speech enhancement in hearing aids and many more. Newest video conferencing setups use SSL. The position of a speaker is detected from the difference in the audio waves received by a microphone array. After detection the camera focuses onto the location of the speaker. The human brain is also able to detect the location of a speaker from auditory signals. It uses, among other cues, the difference in amplitude and arrival time of the sound wave at the two ears, called interaural level and time difference. However, the substrate and computational primitives of our brain are different from classical digital computing. Due to its low power consumption of around 20 W and its performance in real time the human brain has become a great source of inspiration for emerging technologies. One of these technologies is neuromorphic hardware which implements the fundamental principles of brain computing identified until today using complementary metal-oxide-semiconductor technologies and new devices. In this work we propose the first neuromorphic closed-loop robotic system that uses the interaural time difference for SSL in real time. Our system can successfully locate sound sources such as human speech. In a closed-loop experiment, the robotic platform turned immediately into the direction of the sound source with a turning velocity linearly proportional to the angle difference between sound source and binaural microphones. After this initial turn, the robotic platform remains at the direction of the sound source. Even though the system only uses very few resources of the available hardware, consumes around 1 W, and was only tuned by hand, meaning it does not contain any learning at all, it already reaches performances comparable to other neuromorphic approaches. The SSL system presented in this article brings us one step closer towards neuromorphic event-based systems for robotics and embodied computing

A Subthreshold Second-Order Integration Circuit for Versatile Synaptic Alpha Kernel and Trace Generation

In neuromorphic hardware the choice of synaptic kernels and trace dynamics are key for the correct system abstraction and representation of information. This paper presents a novel second-order integration circuit for the implementation of traces and kernels, the Second-order Differential Pair Integrator (SoDPI). It provides smooth alpha-kernel shaped responses to spike input in analog subthreshold complementary Metal Oxide Semiconductor (MOS) technology. Our approach utilises two Differential Pair Integrator (DPI) circuits in series to implement an effective current-mode second-order translinear low-pass filter. Theoretical analysis and experimental measurements demonstrate the improved reliability of this design, which offers a promising approach for modelling biological synaptic and neural responses in neuromorphic hardware, as well as improving the stability of integrated on-chip learning systems