Numerical study of thermomechanical fatigue influence of intermetallic compounds in a lead free solder joint

As electronics is increasingly present the reliability of automotive and aircraft equipment is linked to the reliability of electronic boards. Solder bumps are subjected to multiple stresses (e.g. mechanical, thermal, thermo-mechanical, coupled electro-thermal) due to usage conditions. In the scope of RoHS directive, solder joints are made of lead-free alloys. Very promising candidates to replacing standard SnPb solders in electronic assemblies are based on Tin-Silver-Copper alloys, commonly referred to as SAC. The intermetallic compounds (IMC) located at the interfaces of a lead free solder joint form a layer with usually different mechanical properties from the rest of the volume. They depend on the type of finishes and the solder alloy reacting together. The resulting compound is stiffer and more fragile than the solder itself. The IMC are of great concern when it comes to the thermomechanical fatigue characterization of a solder. Indeed, the thickness of the IMC layer increases in function of the exposure duration to high temperature due to atomic diffusion. The whole rigidity of the assembly increases and can lead to some changes in the solder behavior in the vicinity of the interfaces. Fatigue characterization requires to correlate the relevant failure mechanisms of a model in order to be predictive in different conditions. For that purpose, finite element analyses (FEA) must be accurate and representative. Therefore, it has been decided to evaluate the influence of IMC prone to be implemented in simulations. The drifting stiffness, the concentration of stress or the accumulation of viscoplastic strain near the interfaces are the main aspects investigated in this study using two different FE models made in ABAQUS. First, the simulation of a shear test performed on “grooved” single lap shear specimens 1 is used to quantify the error made on the shear modulus with different thicknesses of IMC. This model is also necessary to determine the creep behavior of the lead free solder in another study by fitting the response of such a stack to the experimental curves. A second model composed of a solder ball with its interfacial IMC has been made (cf. Figure 1). It is used to calculate the increasing in global stiffness due to IMC. The final purpose is to highlight the weaknesses to take into account in fatigue life design for which IMC could be responsible. In a final study this model is to be implemented with a proper nonlinear solder material behavior to correlate with thermomechanical fatigue tests of BGA components

Efficient instruction and data caching for high-performance low-power embedded systems

Although multi-threading processors can increase the performance of embedded systems with a minimum overhead, fetching instructions from multiple threads each cycle also increases the pressure on the instruction cache, potentially harming the performance/consumption ratio. Instruction caches are responsible of a high percentage of the total energy consumption of the chip, which for battery-powered embedded devices becomes a critical issue. A direct way to reduce the energy consumption of the first level instruction cache is to decrease its size and associativity. However, demanding applications, and specially applications with several threads running together, might suffer a dramatic performance slow down, or even increase the total energy consumption of the cache hierarchy, due to the extra misses incurred. In this work we introduce iLP-NUCA (Instruction Light Power NUCA), a new instruction cache that replaces the conventional second level cache (L2) and improves the Energy–Delay of the system. We provided iLP-NUCA with a new tree-based transport network-in-cache that reduces both the cache line service latency and the energy consumption, regarding the former LP-NUCA implementation. We modeled in our cycle-accurate simulation environment both conventional instruction hierarchies and iLP-NUCAs. Our experiments show that, running SPEC CPU2006, iLP-NUCA, in comparison with a state–of–the–art high performance conventional cache hierarchy (three cache levels, dedicated L1 and L2, shared L3), performs better and consumes less energy. Furthermore, iLP-NUCA reaches the performance, on average, of a conventional instruction cache hierarchy implementing a double sized L1, independently of the number of threads. This translates into a reduction of the Energy–Delay product of 21%, 18%, and 11%, reaching 90%, 95%, and 99% of the ideal performance for 1, 2, and 4 threads, respectively. These results are consistent for the considered applications distribution, and bigger gains are in the most demanding applications (applications with high instruction cache requirements). Besides, we increase the performance of applications with several threads without being detrimental for any of them. The new transport topology reduces the average service latency of cache lines by 8%, and the energy consumption of its components by 20%

Moving from Reconstruction Resilient Urban Planning for a Bright Future

Today, more than half of Haiti's population calls cities and towns their home, in a major shift from the 1950s when around 90 percent of Haitians lived in the countryside. Urbanization is usually paired with economic growth, increased productivity, and higher living standards, but in Haiti it has taken a different course. Potential benefits have been overshadowed by immense challenges, all of which require immediate action. To better understand the factors that constrain the sustainable and inclusive development of Haitian cities, this Urbanization Review organizes the challenges along three dimensions of urban development namely planning, connecting, and financing. Planning reviews the challenges in supporting resilient growth to create economically vibrant, environmentally sustainable, and livable cities. Connecting focuses on the obstacles of physically linking people to jobs and businesses to markets, while financing focuses on identifying the key capital, governance, and institutional constraints that are hurdles to successful planning and connecting

Exploiting Natural On-chip Redundancy for Energy Efficient Memory and Computing

Power density is currently the primary design constraint across most computing segments and the main performance limiting factor. For years, industry has kept power density constant, while increasing frequency, lowering transistors supply (Vdd) and threshold (Vth) voltages. However, Vth scaling has stopped because leakage current is exponentially related to it. Transistor count and integration density keep doubling every process generation (Moore’s Law), but the power budget caps the amount of hardware that can be active at the same time, leading to dark silicon. With each new generation, there are more resources available, but we cannot fully exploit their performance potential. In the last years, different research trends have explored how to cope with dark silicon and unlock the energy efficiency of the chips, including Near-Threshold voltage Computing (NTC) and approximate computing. NTC aggressively lowers Vdd to values near Vth. This allows a substantial reduction in power, as dynamic power scales quadratically with supply voltage. The resultant power reduction could be used to activate more chip resources and potentially achieve performance improvements. Unfortunately, Vdd scaling is limited by the tight functionality margins of on-chip SRAM transistors. When scaling Vdd down to values near-threshold, manufacture-induced parameter variations affect the functionality of SRAM cells, which eventually become not reliable. A large amount of emerging applications, on the other hand, features an intrinsic error-resilience property, tolerating a certain amount of noise. In this context, approximate computing takes advantage of this observation and exploits the gap between the level of accuracy required by the application and the level of accuracy given by the computation, providing that reducing the accuracy translates into an energy gain. However, deciding which instructions and data and which techniques are best suited for approximation still poses a major challenge. This dissertation contributes in these two directions. First, it proposes a new approach to mitigate the impact of SRAM failures due to parameter variation for effective operation at ultra-low voltages. We identify two levels of natural on-chip redundancy: cache level and content level. The first arises because of the replication of blocks in multi-level cache hierarchies. We exploit this redundancy with a cache management policy that allocates blocks to entries taking into account the nature of the cache entry and the use pattern of the block. This policy obtains performance improvements between 2% and 34%, with respect to block disabling, a technique with similar complexity, incurring no additional storage overhead. The latter (content level redundancy) arises because of the redundancy of data in real world applications. We exploit this redundancy compressing cache blocks to fit them in partially functional cache entries. At the cost of a slight overhead increase, we can obtain performance within 2% of that obtained when the cache is built with fault-free cells, even if more than 90% of the cache entries have at least a faulty cell. Then, we analyze how the intrinsic noise tolerance of emerging applications can be exploited to design an approximate Instruction Set Architecture (ISA). Exploiting the ISA redundancy, we explore a set of techniques to approximate the execution of instructions across a set of emerging applications, pointing out the potential of reducing the complexity of the ISA, and the trade-offs of the approach. In a proof-of-concept implementation, the ISA is shrunk in two dimensions: Breadth (i.e., simplifying instructions) and Depth (i.e., dropping instructions). This proof-of-concept shows that energy can be reduced on average 20.6% at around 14.9% accuracy loss

Concertina: Squeezing in cache content to operate at near-threshold voltage

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100 percent of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression- and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2 percent, even when using small SRAM cells, which implies over 90 percent of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.Peer ReviewedPostprint (author's final draft

Conservación de los valores arquitectónicos del patrimonio cultural religioso en un sistema antisísmico: El Templo del Señor de Luren de Ica

Se aborda la problemática de la conservación de los valores arquitectónicos utilitarios intrínsecos del patrimonio cultural religioso, con énfasis en la influencia del refuerzo estructural antisísmico. La hipótesis central plantea que este refuerzo permite conservar los valores arquitectónicos, especialmente en aspectos como la acústica y la iluminación. La metodología empleada incluye el análisis de variables como la conservación de los valores arquitectónicos utilitarios intrínsecos, la influencia del refuerzo estructural en el confort acústico y lumínico, y la evaluación de las características físicas de la bóveda central de la iglesia. Se utilizan herramientas como el Simulador PRO, SoundMeter, y LuxMeter, además de entrevistas y modelado 3D para recopilar datos y realizar análisis comparativos. Los resultados indican que el refuerzo estructural ha tenido un impacto mixto. Por un lado, el componente acústico no se conservó adecuadamente, ya que el aumento de la volumetría influyó en el incremento del tiempo de reverberación y la intensidad sonora. Por otro lado, el componente lumínico se conservó parcialmente; la iluminación natural incrementó y se alcanzó un rango de confort lumínico debido al crecimiento del volumen y la reducción de espesores en la bóveda y muros. En conclusión, la tesis establece que, aunque se han logrado ciertos avances en la conservación de los valores lumínicos y acústicos del patrimonio religioso mediante el refuerzo estructural, aún existen desafíos significativos en la preservación integral de estos valores arquitectónicos esenciales. Se observa una necesidad de equilibrar los aspectos estructurales con la conservación de los valores culturales y arquitectónicos intrínsecos del patrimonio

Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping

Cache working-set adaptation is key as embedded systems move to multiprocessor and Simultaneous Multithreaded Architectures (SMT) because interthread pollution harms system performance and battery life. Light-Power NUCA (LP-NUCA) is a working-set adaptive cache that depends on temporal-locality to save energy. This work identifies the sources of energy waste in LP-NUCAs: parallel access to the tag and data arrays of the tiles and low locality phases with useless block migration. To counteract both issues, we prove that switching to serial access reduces energy without harming performance and propose a machine learning Adaptive Drop Rate (ADR) controller that minimizes the amount of replacement and migration when locality is low. This work demonstrates that these techniques efficiently adapt the cache drop and access policies to save energy. They reduce LP-NUCA consumption 22.7% for 1SMT. With interthread cache contention in 2SMT, the savings rise to 29%. Versus a conventional organization, energy--delay improves 20.8% and 25% for 1- and 2SMT benchmarks, and, in 65% of the 2SMT mixes, gains are larger than 20%

Complejo turístico recreacional cultural y paseo paisajístico en el caserío Caracucho - Distrito de Santo Domingo - Provincia de Morropon - Departamento de Piura

En la presente memoria se expone el diseño y creación del proyecto “complejo turístico recreacional cultural y paseo paisajístico”, en el caserío de caracucho ubicado en santo domingo, Morropón, Piura. Este proyecto parte con el estudio y análisis de la problemática de la zona, la cual se basa principalmente, en la necesidad de los pobladores por dejar de depender de actividades agrícolas como principal eje en el desarrollo económico y empezar aprovechar los recursos turísticos con los que cuenta. Para el desarrollo de este proyecto, se inició realizando visitas de campo a la zona e identificando el punto más visitado por los turistas dentro del distrito de santo domingo, siendo el caserío de caracucho y su ancla turísticas conocida como la catarata de caracucho el elegido, relacionándonos directamente con los futuros posibles beneficiarios con la finalidad de conocer sus necesidades con el fin de saber cómo podemos mejorar la calidad de vida de los pobladores locales; a continuación, completaríamos la información obtenida con datos estadísticos y cifras oficiales de la oferta y demanda del turismo local de años anteriores y del sector agroindustrial en general, finalmente logramos cubrir la oferta y demanda actual y hacer un proyección, con la cual se sustenta el proyecto. También analizamos casos nacionales e internacionales de centros interpretación o centros de turismo rural, vivencial o no convencional, que han logrado un éxito notable y los que han fracasado en contextos similares, para tener una perspectiva más amplia del proyecto y lograr comprender el funcionamiento de este equipamiento. Con los datos obtenidos de la fase de investigación, logramos la propuesta de complejo turístico recreacional cultural y paseo paisajístico, en base a la normativa vigente del reglamento nacional de edificaciones en el caso de uso de concreto armado e indagación de técnicas de construcción rurales en pro de una arquitectura sostenible. Con el diseño arquitectónico se logra satisfacer a los distintos usuarios y desarrollar actividades de importancia cultural y recreacional, ya que este equipamiento presenta actividades culturales con un museo, talleres, y auditorio y recinto ferial; recreativas con un restaurant y centro industrial de caña que incluye un área de sembrío; de alojamiento con un hospedaje; y actividades paisajísticas siendo parte del camino hacia la catarata antes mencionada, de la mano con servicios que lo vuelven compatible y sustentable, características que eleven el valor del producto en cuestión, lo cual tiene como consecuencia el desarrollo económico a nivel distrital, provincial y nacional. Finalmente, la propuesta arquitectónica se ha desarrollado en base a reglas básicas para una arquitectura de bajo consumo energético de la mano con principios de una arquitectura sostenible, y en base a un sistema estructural acorde al contexto, además de considerar las instalaciones eléctricas y sanitarias; y las condiciones de seguridad normadas.This report presents the design and creation of the project “Cultural recreational tourist complex and scenic walk”, in the village of Caracucho located in Santo Domingo, Morropón, Piura. This project starts with the study and analysis of the problems of the area which is based mainly on the need of the inhabitants to stop depending on agricultural activities as the main axis in economic development and being to take tourist resources with which bill. For the development of this project, it began by making field visits to the area and identifying the point most visited by tourist within the Santo Domingo district, being the caracucho hamlet and its tourist anchor known as the caracucho waterfall the chosen one. Interacting directly with potential future beneficiaries in order to know their needs in order to know how we can improve the quality of life of local people, next we would complete the information obtained with statistical data and official figures on the supply and demand of local tourism form previous years and the agro-industrial sector in general, finally we were able to cover the current supply and demand and make a projection with which the draft. We also analyze national and international cases of interpretation centers or rural tourism centers, experiential or unconventional, that have achieved notable success and those that have failed in similar contexts, in order to have a broader perspective of the project and to understand how it works. With the data obtained from the research phase, we achieved the proposal of a cultural recreational tourist complex and landscape walk, based on the current regulations of the national building regulations in the case of the use of reinforced concrete and investigation of rural construction techniques in favor of a sustainable architecture. With the architectural design is possible to satisfy the different users and develop activities of cultural and recreational importance, since this facility presents cultural activities with a museum, workshop, and some auditorium fairgrounds; recreational facilities with a restaurant and a sugarcane industrial center that includes a sowing area; of accommodation with a lodging; and landscape activities being part of the road to the aforementioned waterfall, hand in hand with services that make it compatible and sustainable, characteristics that raise the value of the production in question, which has a consequence economic development at the district, provincial and national levels. Finally, the architectural proposal has been developed based on basic rules for an architecture of low energy consumption hand in hand with principles of sustainable architecture, and based on a structural system according to the context, in addition to considering electrical and sanitary installations; and the regulated security conditions.Tesi

Metodología para mejorar la calidad de la entrega continua de proyectos software desplegados sobre plataformas de gestión de contenidos

El proceso de desarrollo de software se encuentra en constante evolución. Por ello, muchas empresas apuestan por la implementación de metodologías de integración y entrega continua en sus proyectos. Esta decisión agiliza los trabajos de detección y depuración de errores, así como asegura unos mínimos de calidad en el producto mediante pruebas en todas las etapas del desarrollo. Hoy en día la gran mayoría de equipos trabajan utilizando un sistema de control de versiones que a su vez se desea que sirva como plataforma para desplegar ese producto. Se hace interesante la idea de poder aunar todo el proceso de desarrollo, revisión y entrega en una misma plataforma, permitiendo un acceso fácil a todas las partes implicadas.Este Trabajo de Fin de Grado estudia el estado actual de la integración y entrega continua en proyectos sobre plataformas de gestión de contenido (CMS) como Drupal en un entorno de trabajo real, y propone la mejora e implantación de una metodología de entrega continua utilizando control de versiones y tecnologías de virtualización. La metodología de entrega continua se implementa mediante el uso de ‘tuberías’ homogéneas sobre el sistema de integración continua de GitLab CI. Este procedimiento incluye la automatización de la ejecución de pruebas de análisis estático, pruebas unitarias, funcionales, seguridad y rendimiento utilizando diferentes frameworks.Este trabajo se ha desarrollado en el ámbito de la empresa Hiberus Digital Business, S.L. Esto ha permitido validar la metodología propuesta sobre un caso real.<br /