Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs

In this work we report an experimental study on accumulation-mode (AM) gate-all-around (GAA) nMOSFETs based on silicon nanowires with uniaxial tensile strain. Their electrical characteristics are studied from room temperature up to ~400 K and carrier mobility, flat-band and threshold voltages are extracted and investigated

Local stressors to accommodate 1.2 to 5.6 GPa uniaxial tensile stress in suspended gate-all-around Si nanowire nMOSFETs by elastic local buckling

In this paper, we demonstrate the integration of local oxidation and metal-gate strain technologies to induce 3.3%/5.6 GPa uniaxial tensile strain/stress in 2 μm long suspended Si nanowire MOSFETs, the highest process-based stress record in MOSFETs until now, by elastic local buckling. Significant stress level modulation in the channel from 1.2 to 5.6 GPa on a single wafer is demonstrated for the first time by varying the NW width. The GAA Si NW MOSFET with 5.6 GPa uniaxial tensile stress is characterized and the electron mobility enhancement is reported

Multigate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility

In this paper, we report for the first time making multi-gate buckled self-aligned dual Si nanowires including two sub-100 nm cross-section cores on bulk Si substrate using optical lithography, hard mask/spacer technology and local oxidation. 0.8 GPa uniaxial tensile stress was measured on the buckled dual nanowires using micro-Raman spectroscopy. The buckled multi-gate dual Si nanowires show excellent electrical characteristics e.g. 62 mV/dec. and 42% low-field electron mobility enhancement due to uniaxial tensile stress in comparison to the non-strained device, all at VDS=50 mV and 293 K

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deplete more electrons than the flat sides or the channel center, when above (local accumulation) and below (local depletion) the flat-band voltage, respectively. On the contrary to the corner effect in the inversion mode (IM) devices, there is no major contribution of corners in the subthreshold current, and therefore, there is no subthreshold device behavior degradation (only one threshold voltage in the system). N-type channel doping levels of 1 x 10(19), 5 x 10(18), and 1 x 10(18) cm(-3) were used for quasi-stationary device simulations of JL and AMMOSFETs, and corner effect was studied for 5, 10, and 15 nm wide equilateral triangular Si NW MOSFETs with a 2 nm SiO2 gate oxide thickness (V-DS = 0 V; T = 300 K). While the local quantum and classical electron density peaks are located in the corner regions above the flat-band voltage, reducing the channel doping and the channel cross-section was found to slightly suppress the normalized total accumulation electron density per unit length, N-acc(t)/(CWeff), in strong accumulation regime

Analog RF and mm-Wave Design Tradeoff in UTBB FDSOI: Application to a 35 GHz LNA

The state-of-the art RF and millimeter-wave first-cut circuits design requires simple hand calculation methods to avoid time-consuming iterative simulations. The classical MOSFET sizing methods used in advanced technologies, still rely on questionable and inaccurate concepts. Moreover, the pessimistic rules of thumb proposed for older bulk technologies are no more useful and lead to overdesign. This work takes advantage of the Moderate Inversion and uses low and high frequency figures of merit to provide a convenient sizing method for a 35 GHz Low Noise Amplifier (LNA) in 28 nm UTBB FDSOI technology

Parish of Wyong, County of Northumberland [cartographic material] : Land District of Gosford, Wyong Shire, Eastern Division N.S.W. /

12th ed. Cadastral map showing parish boundaries and land holdings. Relief shown by spot heights.; "Date of map - 13th January 1850 [ie. 1950]".; Also available in an electronic version via the internet at: http://nla.gov.au/nla.map-vn4041437. Insets: Diagram A, general cemetery at Yarramalong. Scale [ca. 1:6,336] -- Diagram B, Wyong general cemetery. Scale [ca. 1:6,336]

TCAD Simulation of SOI TFETs and Calibration of Non-local Band-to-Band Tunneling Model

This paper reports a simulation based study of the non-local tunneling model using a commercially available technology computer-aided design (TCAD) device simulator. Single gate Tunnel FET devices with 400nm gate length based on SOI technology are measured and compared with simulated data. A step by step algorithm to calibrate the nonlocal Band-to-Band tunneling model implemented in Synopsys Sentaurus TCAD has been shown, demonstrating the importance of model parameters. By using only the reduced mass as the fitting parameter we have obtained a physically meaningful fit with the measured data. The dependence of the tunneling generation rate on the different crystallographic directions is also demonstrated for the first time