The new monolithic ASIC of the preshower detector for di-photon measurements in the FASER experiment at CERN

The ForwArd Search ExpeRiment (FASER) is an experiment searching for new light and weakly-interacting particles at CERN's Large Hadron Collider. FASER is composed of different sub-detectors, including silicon microstrip detectors, scintillator counters and an electromagnetic calorimeter. In this paper, a new preshower detector for the FASER experiment is presented. The new detector, based on monolithic pixel ASICs, will provide excellent spatial and time resolutions and a large charge dynamic range. First results from a prototype chip produced by IHP in 130 nm SiGe BiCMOS technology are shown

Replacing full custom DAQ test system by COTS DAQ components on example of ATLAS SCT readout

A test system developed for ABCN-25 for ATLAS Inner Detector Upgrade is presented. The system is based on commercial off the shelf DAQ components by National Instruments and foreseen to aid in chip characterization and hybrid/module development complementing full custom VME based setups. The key differences from the point of software development are presented, together with guidelines for developing high performance LabVIEW code. Some real-world benchmarks will also be presented together with chip test results. The presented tests show good agreement of test results between the test setups used in different sites, as well as agreement with design specifications of the chip

SO(10) unified models and soft leptogenesis

Motivated by the fact that, in some realistic models combining SO(10) GUTs and flavour symmetries, it is not possible to achieve the required baryon asymmetry through the CP asymmetry generated in the decay of right-handed neutrinos, we take a fresh look on how deep this connection is in SO(10). The common characteristics of these models are that they use the see-saw with right-handed neutrinos, predict a normal hierarchy of masses for the neutrinos observed in oscillating experiments and in the basis where the right-handed Majorana mass is diagonal, the charged lepton mixings are tiny. In addition these models link the up-quark Yukawa matrix to the neutrino Yukawa matrix Y^\nu with the special feature of Y^\nu_{11}-> 0 Using this condition, we find that the required baryon asymmetry of the Universe can be explained by the soft leptogenesis using the soft B parameter of the second lightest right-handed neutrino whose mass turns out to be around 10^8 GeV. It is pointed out that a natural way to do so is to use no-scale supergravity where the value of B ~1 GeV is set through gauge-loop corrections.Comment: 26 pages, 2 figures. Added references, new appendix of a relevant fit and improved comment

CP and Lepton-Number Violation in GUT Neutrino Models with Abelian Flavour Symmetries

We study the possible magnitudes of CP and lepton-number-violating quantities in specific GUT models of massive neutrinos with different Abelian flavour groups, taking into account experimental constraints and requiring successful leptogenesis. We discuss SU(5) and flipped SU(5) models that are consistent with the present data on neutrino mixing and upper limits on the violations of charged-lepton flavours and explore their predictions for the CP-violating oscillation and Majorana phases. In particular, we discuss string-derived flipped SU(5) models with selection rules that modify the GUT structure and provide additional constraints on the operators, which are able to account for the magnitudes of some of the coefficients that are often set as arbitrary parameters in generic Abelian models.Comment: 30 pages, 6 figure

Time resolution and power consumption of a monolithic silicon pixel prototype in SiGe BiCMOS technology

SiGe BiCMOS technology can be used to produce ultra-fast, low-power silicon pixel sensors that provide state-of-the-art time resolution even without an internal gain mechanism. The development of such sensors requires the identification of the main factors that may degrade the timing performance and the characterisation of the dependance of the sensor time resolution on the amplifier power consumption. Measurements with a $\mathrm{^{90}Sr}$ source of a prototype sensor produced in SG13G2 technology from IHP Microelectronics, shows a time resolution of 140 ps at an amplifier current of 7 $\mathrm{\mu}$A and 45 ps at higher power consumption. A full simulation shows that the resolution on the measurement of the signal time-over-threshold, used to correct for time walk, is the main factor affecting the timing performance

HV/HR-CMOS sensors for the ATLAS upgrade—concepts and test chip results

In order to extend its discovery potential, the Large Hadron Collider (LHC) will have a major upgrade (Phase II Upgrade) scheduled for 2022. The LHC after the upgrade, called High-Luminosity LHC (HL-LHC), will operate at a nominal leveled instantaneous luminosity of 5× 1034 cm−2 s−1, more than twice the expected Phase I . The new Inner Tracker needs to cope with this extremely high luminosity. Therefore it requires higher granularity, reduced material budget and increased radiation hardness of all components. A new pixel detector based on High Voltage CMOS (HVCMOS) technology targeting the upgraded ATLAS pixel detector is under study. The main advantages of the HVCMOS technology are its potential for low material budget, use of possible cheaper interconnection technologies, reduced pixel size and lower cost with respect to traditional hybrid pixel detector. Several first prototypes were produced and characterized within ATLAS upgrade R&D effort, to explore the performance and radiation hardness of this technology. In this paper, an overview of the HVCMOS sensor concepts is given. Laboratory tests and irradiation tests of two technologies, HVCMOS AMS and HVCMOS GF, are also given

Radiation-hard active pixel sensors for HL-LHC detector upgrades based on HV-CMOS technology

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown