LArPix: Demonstration of low-power 3D pixelated charge readout for liquid argon time projection chambers

We report the demonstration of a low-power pixelated readout system designed for three-dimensional ionization charge detection and digital readout of liquid argon time projection chambers (LArTPCs). Unambiguous 3D charge readout was achieved using a custom-designed system-on-a-chip ASIC (LArPix) to uniquely instrument each pad in a pixelated array of charge-collection pads. The LArPix ASIC, manufactured in 180 nm bulk CMOS, provides 32 channels of charge-sensitive amplification with self-triggered digitization and multiplexed readout at temperatures from 80 K to 300 K. Using an 832-channel LArPix-based readout system with 3 mm spacing between pads, we demonstrated low-noise ($<$500 e$^-$ RMS equivalent noise charge) and very low-power ($<$100 $\mu$W/channel) ionization signal detection and readout. The readout was used to successfully measure the three-dimensional ionization distributions of cosmic rays passing through a LArTPC, free from the ambiguities of existing projective techniques. The system design relies on standard printed circuit board manufacturing techniques, enabling scalable and low-cost production of large-area readout systems using common commercial facilities. This demonstration overcomes a critical technical obstacle for operation of LArTPCs in high-occupancy environments, such as the near detector site of the Deep Underground Neutrino Experiment (DUNE).Comment: 19 pages, 10 figures, 1 ancillary animation. V3 includes minor revisions based on referee comment

Electrical Properties of Carbon Fiber Support Systems

Carbon fiber support structures have become common elements of detector designs for high energy physics experiments. Carbon fiber has many mechanical advantages but it is also characterized by high conductivity, particularly at high frequency, with associated design issues. This paper discusses the elements required for sound electrical performance of silicon detectors employing carbon fiber support elements. Tests on carbon fiber structures are presented indicating that carbon fiber must be regarded as a conductor for the frequency region of 10 to 100 MHz. The general principles of grounding configurations involving carbon fiber structures will be discussed. To illustrate the design requirements, measurements performed with a silicon detector on a carbon fiber support structure at small radius are presented. A grounding scheme employing copper-kapton mesh circuits is described and shown to provide adequate and robust detector performance.Comment: 20 pages, 11 figures, submitted to NI

Integrated Circuit Design in US High-Energy Physics

This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies; Outlook of future technologies including 2.5D and 3D; Survey of ICs used in current experiments and ICs targeted for approved or proposed experiments; IC design at US institutes and recommendations for collaboration in the future

3D electronics for hybrid pixel detectors – TWEPP-09

Future hybrid pixel detectors are asking for smaller pixels in order to improve spatial resolution and to deal with an increasing counting rate. Facing these requirements is foreseen to be done by microelectronics technology shrinking. However, this straightforward approach presents some disadvantages in term of performances and cost. New 3D technologies offer an alternative way with the advantage of technology mixing. For the upgrade of ATLAS pixel detector, a 3D conception of the read-out chip appeared as an interesting solution. Splitting the pixel functionalities into two separate levels will reduce pixel size and open the opportunity to take benefit of technology's mixing. Based on a previous prototype of the read-out chip FE-I4 (IBM 130nm), this paper presents the design of a hybrid pixel read-out chip using threedimensional Tezzaron-Chartered technology. In order to disentangle effects due to Chartered 130nm technology from effects involved by 3D architecture, a first translation of FEI4 prototype had been designed at the beginning of this year in Chartered 2D technology, and first test results will be presented in the last part of this paper

Low power discriminator for ATLAS pixel chip

The design of the front-end (FE) pixel electronics requires low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the presence of a signal at the input of the discriminator. Since the activity in the FE chip is very low, the power consumption is largely reduced allowing the material reduction in the B-layer

HV/HR-CMOS sensors for the ATLAS upgrade—concepts and test chip results

In order to extend its discovery potential, the Large Hadron Collider (LHC) will have a major upgrade (Phase II Upgrade) scheduled for 2022. The LHC after the upgrade, called High-Luminosity LHC (HL-LHC), will operate at a nominal leveled instantaneous luminosity of 5× 1034 cm−2 s−1, more than twice the expected Phase I . The new Inner Tracker needs to cope with this extremely high luminosity. Therefore it requires higher granularity, reduced material budget and increased radiation hardness of all components. A new pixel detector based on High Voltage CMOS (HVCMOS) technology targeting the upgraded ATLAS pixel detector is under study. The main advantages of the HVCMOS technology are its potential for low material budget, use of possible cheaper interconnection technologies, reduced pixel size and lower cost with respect to traditional hybrid pixel detector. Several first prototypes were produced and characterized within ATLAS upgrade R&#38;D effort, to explore the performance and radiation hardness of this technology. In this paper, an overview of the HVCMOS sensor concepts is given. Laboratory tests and irradiation tests of two technologies, HVCMOS AMS and HVCMOS GF, are also given

Radiation-hard active pixel sensors for HL-LHC detector upgrades based on HV-CMOS technology

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for the ring-oscillator based Voltage Controlled Oscillator (VCO) is fVCO = 640MHz. The last sections deal with a fabricated demonstrator that provides the option of feeding the single-ended 80MHz output clock of the PLL as a clock signal to a digital test logic block integrated on-chip. The digital logic consists of an eight bit pseudo-random binary sequence generator, an eight bit to ten bit coder and a serializer. It processes data with a speed of 160 Mbit/s. All dynamic signals are driven off-chip by custommade pseudo-LVDS drivers