A compositional model for synchronous VLSI systems

technical reportCurrently available hardware specification languages have two serious deficiencies: (i) inadequate protocol definition capabilities; (ii) lack of a compositional model. We now explain these in more detail

Formal methods for surviving the jungle of heterogeneous parallelism

pre-printThe parallel programming community will soon be entering the ‘jungle' of heterogeneous hardware and software. Unfortunately, we are not adequately preparing future programmers (today's students) to cope with the many challenges of heterogeneous concurrency, especially in their ability to rigorously specify and verify concurrent systems. Concerted action is urgently needed to create a body of education material supplemented by effective software tools that help gain working knowledge of specification and verification techniques. We suggest funding models and incentives that can help create this material and put them into wide practice

HOP: A formal model for synchronous circuits using communicating fundamental mode symbolic automata

technical reportWe study synchronous digital circuits in an abstract setting. A circuit is viewed as a collection of modules connected through their boundary ports, where each port assumes a fixed direction (input or output) over one cycle of operation, and can change directions across cycles. No distinction is made between clock inputs and non-clock inputs. A cycle of operation consists of the application of a set of inputs followed by the stabilization of the module state before the next inputs are applied (i.e. fundamental mode operation is assumed). The states and inputs of a module are modeled symbolically, in a functional notation. This enables us to study not only finite-state controllers, but also large data paths, possibly with unbounded amounts of state. We present the abstract syntax for modules, well-formedness checks on the syntax, the formal semantics in terms of the denotation of a module, and the rule for composing two modules interconnected and operating in parallel, embodied in the operator par. It is shown that par preserves well-formedness, and denotes conjunction. These results are applicable to virtually every kind of synchronous circuit (e.g. VLSI circuits that employ single or multiphase clocks, circuits that employ switch or gate logic structures, circuits that employ uni- or bi-directional ports, etc.), thanks to the small number of assumptions upon which the HOP model is set up

Asynchronous circuit verification using trace theory and CCS

technical reportWe investigate asynchronous circuit verification using Dill's trace theory as well as Milner's CCS (as mechanized by the Concurrency Workbench). Trace theory is a formalism specifically designed for asynchronous circuit specification and verification. CCS is a general purpose calculus of communicating systems that is recently being applied for hardware specification and verification also. Although both formalisms are similar in many respects, we find that there are many interesting differences between them when applied to asynchronous circuit specification and verification. The purpose of this paper is to point out these differences, many of which are precautions for avoiding writing incorrect specifications. A long-term objective of this work is to find a way to take advantage of the strengths of both the Trace Theory verifier and the Concurrency Workbench in verifying asynchronous circuits

An integration of dynamic MPI formal verification within eclipse PTP

PosterOur research goals were to verify practical MPI programs for deadlocks, resource leaks, and assertion violations at the push of a button and be able to easily visualize the results. We also sought to integrate these capabilities with the Eclipse IDE via an Eclipse plug-in for the Parallel Tools Platform (PTP). We present here the result of our work, GEM - Graphical Explorer of MPI

Some unusual micropipeline circuits

Journal ArticleWe present a few unusual Micropipelines (Sutherland, CACM, September 1989) that employ the Muller C-ELEMENT or an extension of the C-ELEMENT called LOCKC (Liebchen and Gopalakrishnan, ICCD, 1992). We first describe two variations of the two-dimensional Micropipeline structure realized using ordinary C-ELEMENTs. These micropipelines can be used to control wavefront arrays (S.-Y.Kung et.al, IEEE Computer, 1987). Next, we present a ring style arbiter realized using a LocKC-based one-dimensional micropipeline. Finally, we present a solution to the symmetric crossbar arbitration problem posed by Tamir and Chi (IEEE Trans. Parallel and Dist Systems, Jan '93) using a circuit that employs the two-dimensional micropipeline as well as the LOCKC. We present various circuits to solve the symmetric crossbar arbitration problem, including ones that consume very little power when idling

The 'test model-checking' approach to the verification of formal memory models of multiprocessors

technical reportWe offer a solution to the problem of verifying formal memory models of processors by com bining the strengths of model checking and a formal testing procedure for parallel machines We characterize the formal basis for abstracting the tests into test automata and associated memory rule safety properties whose violations pinpoint the ordering rule being violated Our experimen tal results on Verilog models of a commercial split transaction bus demonstrates the ability of our method to e??ectively debug design models during early stages of their developmen

A partial order reduction algorithm without the Proviso

Journal ArticleThis paper presents a partial order reduction algorithm, called Two phase, that preserves stutter free LTL properties. Two phase dramatically reduces the number of states visited compared to previous partial order reduction algorithms on most practical protocols. The reason can be traced to a step of the previous algorithms, called the proviso step, that specifies a condition on how a state that closes a loop is expanded. Two phase can be easily combined with an on-the-fly model-checking algorithm to reduce the memory requirements further. Furthermore a simple but powerful selective-caching scheme can also be added to Two phase. Two phase has been implemented in a model-checker called PV (Protocol Verifier) and is in routine use on large problems

Ovis: A framework for visual analysis of ocean forecast ensembles

pre-printWe present a novel integrated visualization system that enables interactive visual analysis of ensemble simulations of the sea surface height that is used in ocean forecasting. The position of eddies can be derived directly from the sea surface height and our visualization approach enables their interactive exploration and analysis.The behavior of eddies is important in different application settings of which we present two in this paper. First, we show an application for interactive planning of placement as well as operation of off-shore structures using real-world ensemble simulation data of the Gulf of Mexico. Off-shore structures, such as those used for oil exploration, are vulnerable to hazards caused by eddies, and the oil and gas industry relies on ocean forecasts for efficient operations. We enable analysis of the spatial domain, as well as the temporal evolution, for planning the placement and operation of structures.Eddies are also important for marine life. They transport water over large distances and with it also heat and other physical properties as well as biological organisms. In the second application we present the usefulness of our tool, which could be used for planning the paths of autonomous underwater vehicles, so called gliders, for marine scientists to study simulation data of the largely unexplored Red Sea