A 16-channel Digital TDC Chip with internal buffering and selective readout for the DIRC Cherenkov counter of the BABAR experiment

A 16-channel digital TDC chip has been built for the DIRC Cherenkov counter of the BaBar experiment at the SLAC B-factory (Stanford, USA). The binning is 0.5 ns, the conversion time 32 ns and the full-scale 32 mus. The data driven architecture integrates channel buffering and selective readout of data falling within a programmable time window. The time measuring scale is constantly locked to the phase of the (external) clock. The linearity is better than 80 ps rms. The dead time loss is less than 0.1% for incoherent random input at a rate of 100 khz on each channel. At such a rate the power dissipation is less than 100 mw. The die size is 36 mm2.Comment: Latex, 18 pages, 13 figures (14 .eps files), submitted to NIM

Silicon Data Acquisition and Front-End Electronics

A highly integrated Front-End readout and Data Acquisition scheme for Silicon trackers is presented. In this context, a 16-channel readout chip for Silicon strips detector has been designed in 180nm CMOS technology, having in view a highly multiplexed and sparsified readout global strategy. First results are presented

Front-End and Readout Electronics for Silicon Trackers at the ILC

A highly integrated readout scheme for Silicon trackers making use of Deep Sub-Micron CMOS electronics is presented. In this context,a 16-channel readout chip for Silicon strips detector has been designed in 180nm CMOS technology, each channel comprising a low noise amplifier, a pulse shaper, a sample and hold and a comparator. First results are presented

A 96-Channel FPGA-based Time-to-Digital Converter

We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) in the CDF Experiment at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGA's. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 $\mu$s allow deadtime-less operation in the first-level trigger. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/sec. The TDC also contains a separately-programmed data path that produces prompt trigger data every Tevatron crossing. The full TDC design and multi-card test results are described. The physical simplicity ensures low-maintenance; the functionality being in firmware allows reprogramming for other applications.Comment: 32 pages, 13 figure

Development of a sampling ASIC for fast detector signals

International audienceIn the context of the Large Area Picosecond Photodetector (LAPPD) pro ject the motivation to measure time-of-flight at the picosecond reso- lution has pushed towards a faster signal rise-time (below 100 ps) and a higher bandwidth output (higher than 1 GHz) detector, thus, leading to a new signal development and integrity studies of Micro-Channel Plates (MCP) photo-detectors. Similarly, the signal path, is being simulated and characterized, from the anodes to the input of the readout electronics, to minimise losses. Furthermore, to acquire the detector fast pulses a new 10 Gs/s high input bandwidth, 130 nm CMOS sampling chip is being de- veloped

Front-end Electronics for Silicon Trackers readout in Deep Sub-Micron CMOS Technology: The case of Silicon strips at the ILC

For the years to come, Silicon strips detectors will be read using the smallest available integrated technologies for room, transparency, and power considerations. CMOS, Bipolar- CMOS and Silicon-Germanium are presently offered in deepsubmicron (250 down to 90nm) at affordable cost through worldwide integrated circuits multiproject centers. As an example, a 180nm CMOS readout prototype chip has been designed and tested, and gave satisfactory results in terms of noise and power. Beam tests are under work, and prospectives in 130nm will be presented

Search for microwave emission from ultrahigh energy cosmic rays

We present a search for microwave emission from air showers induced by ultrahigh energy cosmic rays with the microwave detection of air showers experiment. No events were found, ruling out a wide range of power flux and coherence of the putative emission, including those suggested by recent laboratory measurements.Comment: 5 pages, 3 figure

The MIDAS experiment: A prototype for the microwave emission of Ultra-High Energy Cosmic Rays

Recent measurements suggest that extensive air showers initiated by ultra-high energy cosmic rays (UHECR) emit signals in the microwave band of the electromagnetic spectrum caused by the collisions of the free-electrons with the atmospheric neutral molecules in the plasma produced by the passage of the shower. Such emission is isotropic and could allow the detection of air showers with 100% duty cycle and a calorimetric-like energy measurement, a significant improvement over current detection techniques. We have built MIDAS (MIcrowave Detection of Air Showers), a prototype of microwave detector, which consists of a 4.5 m diameter antenna with a cluster of 53 feed-horns in the 4 GHz range. The details of the prototype and first results will be presented.Comment: To appear in the proceedings of 12th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD10), Siena, Italy, 7 - 10 June 201

A CMOS 130nm Evaluation digitzer chip for silicon strips readout

A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and parallel analogue to digital conversion. Tests results of the full chain are reported, demonstrating the behaviour and performance of the full sampling process and analogue to digital conversion. Each channel dissipates less than one milli-Watt static power