Chaos and convergence of a family generalizing Homeier's method with damping parameters

[EN] In this paper, a family of parametric iterative methods for solving nonlinear equations, including Homeier's scheme, is presented. Its local convergence is obtained and the dynamical behavior on quadratic polynomials of the resulting family is studied in order to choose those values of the parameter that ensure stable behavior. To get this aim, the analysis of fixed and critical points and the associated parameter plane show the dynamical richness of the family and allow us to find members of this class with good numerical properties and also other ones with pathological conduct. To check the stable behavior of the good selected ones, the discretized planar 1D-Bratu problem is solved. Some of those chosen members of the family achieve good results when Homeier's scheme fails.This research was supported by Ministerio de Economia y Competitividad MTM2014-52016-C02-2-P.Cordero Barbero, A.; Franques, A.; Torregrosa Sánchez, JR. (2016). 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Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding on the wireless intra-chip channel. This paper first demonstrates that such assumptions do not hold in the context of commercial chips by evaluating losses and dispersion in them. Then, we leverage the system's monolithic nature to engineer the channel, this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it, pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce the path loss and delay spread of a simulated commercial chip by 47 dB and 7.3x, respectively, enabling intra-chip wireless communications over 10 Gb/s and only 3.1 dB away from the dispersion-free case.Comment: 12 pages, 10 figures. IEEE Transactions on Communications Journal, 202

Millimeter-wave propagation within a computer chip package

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. The WNoC paradigm has been extensively analyzed from the physical, network and architecture perspectives assuming mmWave band operation. However, there has not been a comprehensive study at this band for realistic chip packages and, thus, the characteristics of such wireless channel remain not fully understood. This work addresses this issue by accurately modeling a flip-chip package and investigating the wave propagation inside it. Through parametric studies, a locally optimal configuration for 60 GHz WNoC is obtained, showing that chip-wide attenuation below 32.6 dB could be achieved with standard processes. Finally, the applicability of the methodology is discussed for higher bands and other integrated environments such as a Software-Defined Metamaterial (SDM).Peer ReviewedPostprint (author's final draft

Engineer the channel and adapt to it: enabling wireless intra-chip communication

© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The authors gratefully acknowledge support from the Spanish MINECO under grant PCIN-2015-012, from the EU’s H2020 FET-OPEN program under grants No. 736876 and No. 863337, and by the Catalan Institution for Research and Advanced Studies (ICREA).Peer ReviewedPostprint (author's final draft

On-chip wireless manycore architectures

Recent computer architecture trends herald the arrival of massive multiprocessors with more than a hundred processor cores within a single package. In this setting, on-chip communication becomes increasingly important, as parallel programs increase the amount of data sharing and signaling between cores. Unfortunately, traditional on-chip networks have been proven to not scale well in terms of latency or energy consumption, slowing down the computation, and jeopardizing the scalability of hundred-core processors. On-chip wireless networks are a novel interconnect paradigm that holds considerable promise for overcoming the communication challenges left unmet by wired networks-on-chip, and for enabling such massive multicore chips. In this thesis, we propose several applications of on-chip wireless technology for manycore architectures, namely: Replica, a manycore that uses wireless communication for synchronization and communication-intensive data; WiDir, which uses on-chip wireless technology to augment a conventional invalidation-based directory cache coherence protocol; and WiChip, a chiplet-based architecture that uses a wireless network to attain scalable communication. Besides the aforementioned applications of on-chip wireless technology, in this thesis we also address some of the challenges that come with the technology. One of the main challenges of on-chip wireless technology is the design of methods that provide fast and efficient access to the wireless channel while adapting to the constant traffic changes within and across applications. Hence, we propose Fuzzy-Token, a simple medium access control protocol that leverages the unique properties of the on-chip scenario to deliver efficient and low-latency access irrespective of the application characteristics.U of I OnlyAuthor requested U of Illinois access only (OA after 2yrs) in Vireo ETD syste

Fuzzy-token: An adaptive Mac protocol for wireless network-on-chip

Recent computer architecture trends herald the arrival of massive multiprocessors with more than a thousand processor cores within a single chip. In this context, as parallel programs continue to increase the amount of data sharing and signaling between cores, on-chip communication becomes a critical issue. Unfortunately, traditional on-chip networks have been proven to not scale well in terms of latency or energy consumption, slowing down the computation in thousand-core processors. The Wireless Network-on-Chip (WNoC) paradigm holds considerable promise for the implementation of on-chip networks that will enable such massive multicore chips. One of the main challenges, however, resides in the design of methods that provide fast and efficient access to the wireless channel while adapting to the constant traffic changes within and across applications. Existing approaches are either cumbersome or do not provide the required adaptivity. We propose Fuzzy-Token, a simple protocol that leverages the unique properties of the on-chip scenario to deliver efficient and low-latency access irrespective of the application characteristics. We substantiate our claim via simulations with a synthetic traffic suite and real application traces.U of I OnlyAuthor requested U of Illinois access only (OA after 2yrs) in Vireo ETD syste

Fuzzy-token: An adaptive Mac protocol for wireless network-on-chip

Recent computer architecture trends herald the arrival of massive multiprocessors with more than a thousand processor cores within a single chip. In this context, as parallel programs continue to increase the amount of data sharing and signaling between cores, on-chip communication becomes a critical issue. Unfortunately, traditional on-chip networks have been proven to not scale well in terms of latency or energy consumption, slowing down the computation in thousand-core processors. The Wireless Network-on-Chip (WNoC) paradigm holds considerable promise for the implementation of on-chip networks that will enable such massive multicore chips. One of the main challenges, however, resides in the design of methods that provide fast and efficient access to the wireless channel while adapting to the constant traffic changes within and across applications. Existing approaches are either cumbersome or do not provide the required adaptivity. We propose Fuzzy-Token, a simple protocol that leverages the unique properties of the on-chip scenario to deliver efficient and low-latency access irrespective of the application characteristics. We substantiate our claim via simulations with a synthetic traffic suite and real application traces.U of I OnlyAuthor requested U of Illinois access only (OA after 2yrs) in Vireo ETD syste

Fuzzy-Token: An adaptive MAC protocol for wireless-enabled manycores

Recent computer architecture trends herald the arrival of manycores with over one hundred cores on a single chip. In this context, traditional on-chip networks do not scale well in latency or energy consumption, leading to bottlenecks in the execution. The Wireless Network-on-Chip (WNoC) paradigm holds considerable promise for the implementation of on-chip networks that will enable such highly-parallel manycores. However, one of the main challenges in WNoCs is the design of mechanisms that provide fast and efficient access to the wireless channel, while adapting to the changing traffic patterns within and across applications. Existing approaches are either slow or complicated, and do not provide the required adaptivity. In this paper, we propose FUZZY TOKEN, a simple WNoC protocol that leverages the unique properties of the on-chip scenario to deliver efficient and low-latency access to the wireless channel irrespective of the application characteristics. We substantiate our claim via simulations with a synthetic traffic suite and with real application traces. FUZZY TOKEN consistently provides one of the lowest packet latencies among the evaluated WNoC MAC protocols. On average, the packet latency in FUZZY TOKEN is 4.4× and 2.6× lower than in a state-of-the art contention-based WNoC MAC protocol and in a token-passing protocol, respectively.This work was funded in part by NSF Grant No. CCF-1629431 and by EU’s Horizon 2020 research and innovation programme Grant No. 863337 (WiPLASH).Peer ReviewedPostprint (author's final draft

Replica: a wireless manycore for communication-intensive and approximate data

Data access patterns that involve fine-grained sharing, multicasts, or reductions have proved to be hard to scale in sharedmemory platforms. Recently, wireless on-chip communication has been proposed as a solution to this problem, but a previous architecture has used it only to speed-up synchronization. An intriguing question is whether wireless communication can be widely effective for ordinary shared data. This paper presents Replica, a manycore that uses wireless communication for communication-intensive ordinary data. To deliver high performance, Replica supports an adaptive wireless protocol and selective message dropping. We describe the computational patterns that leverage wireless communication, programming techniques to restructure applications, and tools that help with automation. Our results show that wireless communication is effective for ordinary data. For 64 cores, Replica obtains a mean speed-up of 1.76x over a conventional machine. The mean speed-up reaches 1.89x if approximate-computing transformations are enabled. The average energy consumption is substantially reduced by 34% (or 38% with approximate transformations), and the area increases only modestly.Peer Reviewe

Replica: a wireless manycore for communication-intensive and approximate data

Data access patterns that involve fine-grained sharing, multicasts, or reductions have proved to be hard to scale in sharedmemory platforms. Recently, wireless on-chip communication has been proposed as a solution to this problem, but a previous architecture has used it only to speed-up synchronization. An intriguing question is whether wireless communication can be widely effective for ordinary shared data. This paper presents Replica, a manycore that uses wireless communication for communication-intensive ordinary data. To deliver high performance, Replica supports an adaptive wireless protocol and selective message dropping. We describe the computational patterns that leverage wireless communication, programming techniques to restructure applications, and tools that help with automation. Our results show that wireless communication is effective for ordinary data. For 64 cores, Replica obtains a mean speed-up of 1.76x over a conventional machine. The mean speed-up reaches 1.89x if approximate-computing transformations are enabled. The average energy consumption is substantially reduced by 34% (or 38% with approximate transformations), and the area increases only modestly.Peer Reviewe