Taxonomic notes on Western Hemisphere Cyrtinini (Coleoptera: Cerambycidae: Lamiinae) including description of two new \u3ci\u3eCyrtinus\u3c/i\u3e LeConte species

Cyrtinus pygmaeus (Haldeman, 1847) (Coleoptera: Cerambycidae: Lamiinae) is redescribed and newly recorded from Mexico. The female of Decarthria stephensii Hope, 1834 is also redescribed, the number of specimens in the type series is corrected, as is the depository of the types, and the species is newly recorded from Dominica. Two new species of Cyrtinus LeConte, 1852 are described from Mexico: C. fisheri Wappes, Santos-Silva and Nascimento; and C. howdeni Wappes, Santos-Silva and Nascimento. A key to species of Decarthria Hope, 1834 (adapted from an earlier key to Cyrtinini) is provided

Non-Gaussian Stochastic Equivalent Linearization Method for Inelastic Nonlinear Systems with Softening Behaviour, under Seismic Ground Motions

A non-Gaussian stochastic equivalent linearization (NSEL) method for estimating the non-Gaussian response of inelastic non-linear structural systems subjected to seismic ground motions represented as nonstationary random processes is presented. Based on a model that represents the time evolution of the joint probability density function (PDF) of the structural response, mathematical expressions of equivalent linearization coefficients are derived. The displacement and velocity are assumed jointly Gaussian and the marginal PDF of the hysteretic component of the displacement is modeled by a mixed PDF which is Gaussian when the structural behavior is linear and turns into a bimodal PDF when the structural behavior is hysteretic. The proposed NSEL method is applied to calculate the response of hysteretic single-degree-of-freedom systems with different vibration periods and different design displacement ductility values. The results corresponding to the proposed method are compared with those calculated by means of Monte Carlo simulation, as well as by a Gaussian equivalent linearization method. It is verified that the NSEL approach proposed herein leads to maximum structural response standard deviations similar to those obtained with Monte Carlo technique. In addition, a brief discussion about the extension of the method to muti-degree-of-freedom systems is presented

Fast jitter tolerance testing for high-speed serial links in post-silicon validation

Post-silicon electrical validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of high-performance computer platforms under current aggressive time-to-market (TTM) commitments. Improvements in signaling methods, circuits, and process technologies have allowed HSIO data rates to scale well beyond 10 Gb/s. Noise and EM effects can create multiple signal integrity problems, which are aggravated by continuously faster bus technologies. The goal of post-silicon validation for HSIO links is to ensure design robustness of both receiver (Rx) and transmitter (Tx) circuitry in real system environments. One of the most common ways to evaluate the performance of a HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) of the link under worst stressing conditions. However, JTOL testing is extremely time-consuming when executed at specification BER considering manufacturing process, voltage, and temperature (PVT) test coverage. In order to significantly accelerate this process, we propose a novel approach for JTOL testing based on an efficient direct search optimization methodology. Our approach exploits the fast execution of a modified golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are found. Our proposed methodology is validated in a realistic industrial server post-silicon validation platform for three different computer HSIO links: SATA, USB3, and PCIe3.ITESO, A.C

PCIe Gen5 Physical Layer Equalization Tuning by Using K-means Clustering and Gaussian Process Regression Modeling in Industrial Post-silicon Validation

Peripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry. The continuously increasing bandwidth demand from new applications has led to the development of the PCIe Gen5, reaching data rates of 32 GT/s. To mitigate undesired channel effects due to such high-speed, the PCIe specification defines an equalization process at the transmitter (Tx) and the receiver (Rx). Current post-silicon validation practices consist of finding an optimal subset of Tx and Rx coefficients by measuring the eye diagrams across different channels. However, these experiments are very time consuming since they require massive lab measurements. In this paper, we use a K-means approach to cluster all available post-silicon data from different channels and feed those clusters to a Gaussian process regression (GPR)-based metamodel for each channel. We then perform a surrogate-based optimization to obtain the optimal tuning settings for the specific channels. Our methodology is validated by measurements of the functional eye diagram of an industrial computer platform.ITESO, A.C

Metabolic engineering for improving anthranilate synthesis from glucose in Escherichia coli

© 2009 Balderas-Hernández et al; licensee BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution Licens