Development of a PCI Express Based Readout Electronics for the XPAD3 X-Ray Photon Counting Image

International audienceXPAD3 is a large surface X-ray photon counting imager with high count rates, large counter dynamics and very fast data readout. Data are readout in parallel by a PCI Express interface using DMA transfer. The readout frame rate of the complete detector comprising 0.5 MPixels amounts to 500 images per second without dead-time

HV/HR-CMOS sensors for the ATLAS upgrade—concepts and test chip results

In order to extend its discovery potential, the Large Hadron Collider (LHC) will have a major upgrade (Phase II Upgrade) scheduled for 2022. The LHC after the upgrade, called High-Luminosity LHC (HL-LHC), will operate at a nominal leveled instantaneous luminosity of 5× 1034 cm−2 s−1, more than twice the expected Phase I . The new Inner Tracker needs to cope with this extremely high luminosity. Therefore it requires higher granularity, reduced material budget and increased radiation hardness of all components. A new pixel detector based on High Voltage CMOS (HVCMOS) technology targeting the upgraded ATLAS pixel detector is under study. The main advantages of the HVCMOS technology are its potential for low material budget, use of possible cheaper interconnection technologies, reduced pixel size and lower cost with respect to traditional hybrid pixel detector. Several first prototypes were produced and characterized within ATLAS upgrade R&D effort, to explore the performance and radiation hardness of this technology. In this paper, an overview of the HVCMOS sensor concepts is given. Laboratory tests and irradiation tests of two technologies, HVCMOS AMS and HVCMOS GF, are also given

Radiation-hard active pixel sensors for HL-LHC detector upgrades based on HV-CMOS technology

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

Design of analog front-ends for the RD53 demonstrator chip

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment

Development of a PCI Express Based Readout Electronics for the XPAD3 X-Ray Photon Counting Image

International audienceXPAD3 is a large surface X-ray photon counting imager with high count rates, large counter dynamics and very fast data readout. Data are readout in parallel by a PCI Express interface using DMA transfer. The readout frame rate of the complete detector comprising 0.5 MPixels amounts to 500 images per second without dead-time

Test Results of the first 3D-IC Prototype Chip Developed in the Framework of HL-SLHC/ATLAS Hybrid Pixel Upgrade

Published in the Journal of Instrumentation (JINST) Proceedings SectionTo face new challenges brought by the upgrades of the Large Hadron Collider at CERN and of ATLAS pixels detector, for which high spatial resolution, very good signal to noise ratio and high radiation hardness are needed, 3D Integrated Technologies are investigated. Commercial offers of such technologies are only very few and the 3D designer's choice is as a consequence strongly constrained. We present here the test results of the first 3D prototype chip developed in the GlobalFoundries 130 nm chips processed by the Tezzaron Company, submitted within the 3D-IC consortium for which a reliable qualification program was developed. Reliability and influence on the integrated devices behavior of Bond Interface (BI) and Through Silicon Via (TSV) connections, both needed for the 3D integration process, has also been addressed by the tests

Experience with 3D integration technologies in the framework of the ATLAS pixel detector upgrade for the HL-LHC

3D technologies are investigated for the upgrade of the ATLAS pixel detector at the HL-LHC. R&D focuses on both, IC design in 3D, as well as on post-processing 3D technologies such as Through Silicon Via (TSV). The first one uses a so-called via first technology, featuring the insertion of small aspect ratio TSV at the pixel level. As discussed in the paper, this technology can still present technical challenges for the industrial partners. The second one consists of etching the TSV via last. This technology is investigated to enable 4-side abuttable module concepts, using today's pixel detector technology. Both approaches are presented in this paper and results from first available prototypes are discussed

Performance and Applications of the CdTe- and Si-XPAD3 photon counting 2D detector

International audienceThe XPAD3 is the third generation of a single photon counting chip developed in collaboration by SOLEIL Synchrotron, the Institut Néel and the Centre de Physique de Particules de Marseille (CPPM). The chip contains 9600 pixels of 130 mmside and a counting electronic chain with an adjustable low level threshold in each pixel. Imaging and detection performance (detective quantum efficiency, modulation transfer function and energy resolution) of the XPAD3 detectors hybridized with Si and CdTe sensors have been evaluated and compared using monochromatic synchrotron X-rays beam. A second version of the chip, optimized for pump-probe experiments, has been realized and successfully tested. Three 7.3 cm x 12.5 cm Si-XPAD3 imagers, composed of 8 silicon modules (7 chips per module) and one 2.1 cm x 3.1 cm CdTe-XPAD3 imager (4 chips) have been constructed and successfully used for synchrotron diffraction experiments and biomedical imaging