Extended models of Coulomb scattering for the Monte Carlo simulation of nanoscale silicon MOSFETs

The International Technology Roadmap for Semiconductors (ITRS) specifies that MOSFET logic devices are to be scaled to sub-10nm dimensions by the year 2020, with 32nm bulk devices ready for production and double-gate FinFET devices demonstrated down to 5nm channel lengths. Future device generations are expected to have lower channel doping in order to reduce variability in devices due to the discrete nature of the channel dopants. Accompanying the reduced channel doping is a corresponding increase in the screening length, which is even now comparable with the channel length. Under such conditions, Coulomb scattering mechanisms become increasingly complex as the scattering potential interacts with a larger proportion of the device. Ionized impurity scattering within the channel is known to be an important Coulombic scattering mechanism within MOSFETs. Those channel impurities located close to the heavily doped source and drain or both, will induce a polarisation charge within the source and drain. These polarisation charge effects are shown in this work to increase the net screening of the channel impurities, due to the inclusion of remote screening effects, and significantly decrease the scattering rate associated with ionized impurity scattering. Remote screening can potentially reduce the control by ionized channel impurities over channel transport properties, leading to an increased sub-threshold current. A potential model has been obtained that is based on an exact solution of Poisson’s equation for an ionized impurity located close to one or both of these highly doped contact regions. The model shows that remote screening effects are evident within a few channel screening lengths of the highly doped contact regions. The resultant scattering model developed from this potential, which is based on the Born approximation, is implemented within a Monte Carlo simulator and is applied to MOSFET device simulation. The newly developed ionized impurity scattering model, which allows for remote screening, is applied in the simulation of two representative MOSFET devices: the first device being a bulk MOSFET device developed for the 32nm technology generation; the second device is an Ultra-Thin-Body Double Gate (UTB DG) MOSFET developed for the forthcoming 22nm technology generation. Thorough investigative simulations show that for both the bulk MOSFET and the UTB DG MOSFET, that remote screening of channel impurities in these devices is not a controlling effect. These results prove that the current model for ionized impurity scattering employed in Monte Carlo simulations is sufficient to model devices scaled to at least the 22nm technology node, predicted to be in production in the year 2012

Interaction Between Precisely Placed Dopants and Interface Roughness in Silicon Nanowire Transistors: Full 3-D NEGF Simulation Study

In this work, we report a theoretical study based on quantum transport simulations that show the impact of the surface roughness on the performance of ultimately scaled gate-all-around silicon nanowire transistors (SNWT) with precisely positioned dopants designed for digital circuit applications. Due to strong inhomogeneity of the self-consistent electrostatic potential, a full 3-D real-space Non Equilibrium Green's Function (NEGF) formalism is used. The individual dopants and the profile of the channel surface roughness act as localized scatters and, hence, the impact on the electron transport is directly correlated to the combined effect of position of the single dopants and surface roughness shape. As a result, a large variation in the IOFF and ION and modest variation of the subthreshold slope are observed in the ID-VG characteristics when comparing devices without surface roughness. The variations of the current-voltage characteristics are analyzed with reference to the behaviour of the transmission coefficients, electron potential and electron concentration along the length of the device. Our calculations provide guidance for a future development of the next generation components with sub-10 nm dimensions for the semiconductor industry

Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-diffusion with nonequilibrium Green functions simulations, we show that quantum effects in the charge distribution and transport can reduce or amplify the impact of discrete traps in simulation of reliability resilience of scaled FinFETs

One-Dimensional Multi-Subband Monte Carlo Simulation of Charge Transport in Si Nanowire Transistors

In this paper, we employ a newly-developed one-dimensional multi-subband Monte Carlo (1DMSMC) simulation module to study electron transport in nanowire structures. The 1DMSMC simulation module is integrated into the GSS TCAD simulator GARAND coupling a MC electron trajectory simulation with a 3D Poisson-2D Schrödinger solver, and accounting for the modified acoustic phonon, optical phonon, and surface roughness scattering mechanisms. We apply the simulator to investigate the effect of the overlap factor, scattering mechanisms, material and geometrical properties on the mobility in silicon nanowire field-effect transistors (NWTs). This paper emphasizes the importance of using 1D models that include correctly quantum confinement and allow for a reliable prediction of the performance of NWTs at the scaling limits. Our simulator is a valuable tool for providing optimal designs for ultra-scaled NWTs, in terms of performance and reliability

Impact of Strain on the Performance of Si Nanowires Transistors at the Scaling Limit: A 3D Monte Carlo/2D Poisson Schrodinger Simulation Study

In this work we investigate the correlation between channel strain and device performance in various n-type Si-NWTs. We establish a correlation between strain, gate length and cross-section dimension of the transistors. For the purpose of this paper we simulate Si NWTs with a <110> channel orientation, four different ellipsoidal channel cross-sections and five gate lengths: 4nm, 6nm, 8nm, 10nm and 12nm. We have also analyzed the impact of strain on drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All simulations are based on a quantum mechanical description of the mobile charge distribution in the channel obtained from a 2D solution of the Schrödinger equation in multiple cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions. The current transport along the channel is simulated using 3D Monte Carlo (MC) and drift-diffusion (DD) approaches

Interactions Between Precisely Placed Dopants and Interface Roughness in Silicon Nanowire Transistors: Full 3-D NEGF Simulation Study

Abstract-In this work, we report a theoretical study based on quantum transport simulations that show the impact of the surface roughness on the performance of ultimately scaled gateall-around silicon nanowire transistors (SNWT) with precisely positioned dopants designed for digital circuit applications. Due to strong inhomogeneity of the self-consistent electrostatic potential, a full 3-D real-space Non Equilibrium Green's Function (NEGF) formalism is used. The individual dopants and the profile of the channel surface roughness act as localized scatters and, hence, the impact on the electron transport is directly correlated to the combined effect of position of the single dopants and surface roughness shape. As a result, a large variation in the I OFF and I O

Experimental and Simulation Study of a High Current 1D Silicon Nanowire Transistor Using Heavily Doped Channels

Silicon nanowires have numerous potential applications, including transistors, memories, photovoltaics, biosensors and qubits [1]. Fabricating a nanowire with the required characteristics for a specific application, however, poses some challenges. For example, a major challenge is that, as the transistors dimensions are reduced, it is difficult to maintain a low off-current (Ioff) whilst simultaneously maintaining a high on-current (Ion). Some sources of this parasitic leakage current include quantum mechanical tunnelling, short channel effects and statistical variability [2, 3]. A variety of new architectures, including ultra-thin silicon-on-insulator (SOI), double gate, FinFETs, tri-gate, junctionless and gate all-around (GAA) nanowire transistors, have therefore been developed to improve the electrostatic control of the conducting channel. This is essential since a low Ioff implies low static power dissipation and it will therefore improve power management in the multi-billion transistors circuits employed globally in microprocessors, sensors and memories

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations <110> and <100> and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90o on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5nm, 6nm, 7nm and 8nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions

Metamorphosis of a nano wire: A 3-D coupled mode space NEGF study

In this paper we present a 3D coupled mode space NEGF study of the quantum features of a nanoscale Gate-All- Around (GAA) silicon transistor. The bottom oxide of the structure is parameterized in order to progressively transform the nanowire in a tri-gate FinFET and the electron transport studied for several Fin widths, back-biases voltages and electron effective masses. Moreover, we address in detail the treatment of the boundary conditions at the channel interface to model the wave function penetration into the gate oxide. We report quantitative results of the charge density obtained by a simplified and a complete discretization approach

Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

The experimental results from 8 nm diameter silicon nanowire junctionless field effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/m for 1.0 V and 2.52 mA/m for 1.8 V gate overdrive with an off-current set at 100 nA/m. On- to off-current ratios above 108 with a subthreshold slope of 66 mV/dec are demonstrated at 25 oC. Simulations using drift-diffusion which include densitygradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength