Application of piecewise-linear switched-capacitor circuits for random number generation

An unconventional application of switched-capacitor (SC) circuits is discussed. A systematic method for the design of piecewise-linear (PL) parasitic-insensitive SC chaotic discrete maps is given. A simple circuit which generates a random one-bit digital sequence is reported. Simulation results show that the random behavior is not significantly altered by large (about 5%) variations in the values of the design parameters, which makes monolithic implementation feasible. Simulation results and layout for a 2- mu m double-metal CMOS prototype are included

Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploitation of current mirror properties for the efficient implementation of both linear and nonlinear analog operators. These cells are simpler and easier to design than those found in previously reported CT and DT-CNN devices. Basic design issues are covered, together with discussions on the influence of nonidealities and advanced circuit design issues as well as design for manufacturability considerations associated with statistical analysis. Three prototypes have been designed for l.6-pm n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. Experimental results are given illustrating performance of these prototypes

Design of an analog/digital truly random number generator

An analog-digital system is presented for the generation of truly random (aperiodic) digital sequences. This model is based on a very simple piecewise-linear discrete map which is suitable for implementation using monolithic analog sampled-data techniques. Simulation results are given illustrating the optimum choice of the model parameters. Circuit implementations are reported for the discrete map using both switched-capacitor (SC) and switched-current (SI) techniques. The layout of a SI prototype in a 3-μm n-well double-polysilicon double-metal technology is included

A Model for VLSI implementation of CNN image processing chips using current-mode techniques

A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. Current-mode building blocks are presented for the design of CMOS image preprocessing chips (feature extraction, noise filtering , compound component detection, etc.) using the cellular neural network paradigm. Area evaluation for the new model shows a reduction off about 50% as compared to the use of current-mode techniques with conventional models. Experimental measurements of CMOS prototypes designed in a 1.6 μm n-well double-metal single-poly technology are reported

Programmable retinal dynamics in a CMOS mixed-signal array processor chip

The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully modelled by a Cellular Neural Network, whose evolution can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of the focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. For these reasons, a programmable array processor prototype chip has been designed and fabricated in a standard 0.5μm CMOS technology. The integrated system consists of a network of two coupled layers, containing 32 × 32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnections weights. Propagative, active wave phenomena and retina-like effects can be observed in this chip. Design challenges, trade-offs, the buildings blocks and some test results are presented in this paper.Office of Naval Research (USA) N00014-00-10429European Community IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT’s connected in a Darlington structure. Pixel smartness is achieved by exploiting the Cellular Neural Network paradigm [1], [2], incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-µm technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm2, with a power consumption down to 105 µW/unit and image processing times below 2 µs

CMOS realization of a 2-layer CNN universal machine chip

Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically coupled layers of locally connected elementary nonlinear processors. In order to explore the possibilities of these complex spatio-temporal dynamics in image processing, a prototype chip has been developed by implementing this CNN model with analog signal processing blocks. This chip has been designed in a 0.5/spl mu/m CMOS technology. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 /spl times/ 10/sup 6/ transistors, most of them operating in analog mode) are presented in this paper.Office of Naval Research (USA) N-00014-00-1-0429Comisión Interministerial de Ciencia y Tecnología TIC-1999-082

Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics

A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the natural visual pathway which renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 /spl mu/m CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5/spl times/10/sup 6/ transistors, most of them operating in analog mode) are presented in this paper.Comisión Interministerial de Ciencia y Tecnología TIC1999-082

Competencia lectora y el aprendizaje en comunicación de estudiantes de sexto grado de primaria en la Institución Educativa Santa María de la Esperanza, Trujillo, 2020

La investigación tuvo como propósito encontrar la relación que existe entre la competencia lectora y el aprendizaje en comunicación de los estudiantes de sexto grado de primaria, en la Institución Educativa “Santa María” de la Esperanza - Trujillo en el año 2020. Esta investigación es de tipo correlacional; se utilizó el diseño no experimental correlacional transversal, se seleccionó a 113 estudiantes con edades de 11 y 12 años entre varones y mujeres. El instrumento y técnica que se utilizó fue la evaluación y la prueba de comprensión lectora respectivamente. Para el proceso y contrastación de hipótesis se utilizó el estadístico de prueba de contraste: Rho de Spearman lo que demostró que existe relación directa, muy fuerte y significativa. Se concluyó que la relación que existe entre la competencia lectora y el aprendizaje en comunicación de los estudiantes de sexto grado de primaria, en la Institución Educativa “Santa María” de la Esperanza- Trujillo en el año 2020 es directa y estadísticamente significativa; así lo demuestran los resultados obtenidos con un coeficiente Rho de Spearman = 0,856 y una prueba altamente significativa, con p – valor = 0.000 < 0.05.Tesi