Eutanasia en pequeños animales

Treball presentat a l'assignatura de Deontologia i Veterinària Legal (21223

Disseny i implementació d'un emulador de xarxa elèctrica

En aquest projecte es presenta el disseny, la implementació i la validació experimental d'un prototip d'emulador de xarxa elèctrica. Un emulador de xarxa elèctrica té com a objectiu recrear certs escenaris sovint imprevisibles en la xarxa elèctrica: variacions de freqüència, contingut harmònic present en l'ona de tensió, desequilibris que pot patir un sistema trifàsic, efecte icker o de parpelleig i els ben coneguts sots de tensió. Un emulador de xarxa té una finalitat molt concreta: Poder sotmetre equips elèctrics o electrònics a qualsevol d'aquests escenaris, de manera que es pugui comprovar quin és el comportament d'aquests equips en front de situacions indesitjables com les que s'han anomenat. Per exemple, comprovar si les proteccions d'un dispositiu electrònic contra certes pertorbacions són efectives i compleixen determinades normatives. Per la implementació de l'anomenat emulador cal recórrer als convertidors d'electrònica de potència. En essència, es tracta de dissenyar un sistema de control digital que, implementat en el convertidor adequat, permeti sintetitzar les formes d'ona de tensió desitjades. En aquest cas, s'utilitzarà un equip de 90 kVA de potència nominal. A més de fer un estudi previ de qualitat elèctrica i d'aspectes relacionats amb convertidors, el present treball es centra en una tècnica de control concreta, els controladors ressonants, dels quals se'n fa un estudi detallat. Seguidament, es presenten unes simulacions exhaustives del sistema, realitzades amb Matlab Simulinkr, pas previ a la implementació real. Finalment, es procedeix a la implementació del codi en el sistema real, mitjançant Code Composer Studior, i a la realització de les proves experimentals per comprovar-ne el correcte funcionament i el seu potencial

Distributed data cache designs for clustered VLIW processors

Wire delays are a major concern for current and forthcoming processors. One approach to deal with this problem is to divide the processor into semi-independent units referred to as clusters. A cluster usually consists of a local register file and a subset of the functional units, while the L1 data cache typically remains centralized in What we call partially distributed architectures. However, as technology evolves, the relative latency of such a centralized cache will increase, leading to an important impact on performance. In this paper, we propose partitioning the L1 data cache among clusters for clustered VLIW processors. We refer to this kind of design as fully distributed processors. In particular; we propose and evaluate three different configurations: a snoop-based cache coherence scheme, a word-interleaved cache, and flexible LO-buffers managed by the compiler. For each alternative, instruction scheduling techniques targeted to cyclic code are developed. Results for the Mediabench suite'show that the performance of such fully distributed architectures is always better than the performance of a partially distributed one with the same amount of resources. In addition, the key aspects of each fully distributed configuration are explored.Peer ReviewedPostprint (published version

Estudi de l'entorn MediaScape

L'objectiu d'aquest projecte és estudiar quines possibilitats ens proporciona el software MediaScape dels laboratoris HP i mirar de desnvolupar una aplicació en l'entorn universitar

Design methodology of the primary droop voltage control for DC microgrids

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.n this article, a complete methodology to design the primary voltage droop control for a generic DC microgrid is proposed. First, a procedure to obtain a linear model of the complete system including the different converters inner and outer loops is detailed. Then, this linear model is analyzed using frequency domain techniques in order to ensure that the system is able to operate in a stable and secure manner. Based on the frequency analysis performed, the system droop gains are selected and tested in simulation to validate that the control design specifications are met.Postprint (author's final draft

Flexible compiler-managed L0 buffers for clustered VLIW processors

Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as clusters. A cluster usually consists of a local register file and a subset of the functional units, while the data cache remains centralized. However, as technology evolves, the latency of such a centralized cache increase leading to an important performance impact. In this paper, we propose to include flexible low-latency buffers in each cluster in order to reduce the performance impact of higher cache latencies. The reduced number of entries in each buffer permits the design of flexible ways to map data from L1 to these buffers. The proposed L0 buffers are managed by the compiler, which is responsible to decide which memory instructions make us of them. Effective instruction scheduling techniques are proposed to generate code that exploits these buffers. Results for the Mediabench benchmark suite show that the performance of a clustered VLIW processor with a unified L1 data cache is improved by 16% when such buffers are used. In addition, the proposed architecture also shows significant advantages over both MultiVLIW processors and clustered processors with a word-interleaved cache, two state-of-the-art designs with a distributed L1 data cache.Peer ReviewedPostprint (published version