Zinc-oxide charge trapping memory cell with ultra-thin chromium-oxide trapping layer

Cataloged from PDF version of article.A functional zinc-oxide based SONOS memory cell with ultra-thin chromium oxide trapping layer was fabricated. A 5 nm CrO2 layer is deposited between Atomic Layer Deposition (ALD) steps. A threshold voltage (Vt) shift of 2.6V was achieved with a 10V programming voltage. Also for a 2V Vt shift, the memory with CrO2 layer has a low programming voltage of 7.2V. Moreover, the deep trapping levels in CrO2 layer allows for additional scaling of the tunnel oxide due to an increase in the retention time. In addition, the structure was simulated using Physics Based TCAD. The results of the simulation fit very well with the experimental results providing an understanding of the charge trapping and tunneling physics. © 2013 Author(s

Silicon nanoparticle charge trapping memory cell

Cataloged from PDF version of article.A charge trapping memory with 2 nm silicon nanoparticles (Si NPs) is demonstrated. A zinc oxide (ZnO) active layer is deposited by atomic layer deposition (ALD), preceded by Al2O3 which acts as the gate, blocking and tunneling oxide. Spin coating technique is used to deposit Si NPs across the sample between Al2O3 steps. The Si nanoparticle memory exhibits a threshold voltage (V-t) shift of 2.9 V at a negative programming voltage of -10 V indicating that holes are emitted from channel to charge trapping layer. The negligible measured V-t shift without the nanoparticles and the good retention of charges (> 10 years) with Si NPs confirm that the Si NPs act as deep energy states within the bandgap of the Al2O3 layer. In order to determine the mechanism for hole emission, we study the effect of the electric field across the tunnel oxide on the magnitude and trend of the V-t shift. The Vt shift is only achieved at electric fields above 1 MV/cm. This high field indicates that tunneling is the main mechanism. More specifically, phonon-assisted tunneling (PAT) dominates at electric fields between 1.2 MV/cm 2.1 MV/cm).(C) 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Enhanced memory effect via quantum confinement in 16 nm InN nanoparticles embedded in ZnO charge trapping layer

Cataloged from PDF version of article.In this work, the fabrication of charge trapping memory cells with laser-synthesized indium-nitride nanoparticles (InN-NPs) embedded in ZnO charge trapping layer is demonstrated. Atomic layer deposited Al2O3 layers are used as tunnel and blocking oxides. The gate contacts are sputtered using a shadow mask which eliminates the need for any lithography steps. High frequency C-Vgate measurements show that a memory effect is observed, due to the charging of the InN-NPs. With a low operating voltage of 4 V, the memory shows a noticeable threshold voltage (Vt) shift of 2 V, which indicates that InN-NPs act as charge trapping centers. Without InN-NPs, the observed memory hysteresis is negligible. At higher programming voltages of 10 V, a memory window of 5 V is achieved and the Vt shift direction indicates that electrons tunnel from channel to charge storage layer. © 2014 AIP Publishing LL

Charge trapping memory with 2.85-nm Si-nanoparticles embedded in HfO<inf>2</inf>

In this work, the effect of embedding 2.85-nm Si-nanoparticles charge trapping layer in between double layers of high-κ Al2O3/HfO2 oxides is studied. Using high frequency (1 MHz) C-Vgate measurements, the memory showed a large memory window at low program/erase voltages due to the charging of the Si-nanoparticles. The analysis of the C-V characteristics shows that mixed charges are being stored in the Si-nanoparticles where electrons get stored during the program operation while holes dominate in the Si-nanoparticles during the erase operation. Moreover, the retention characteristic of the memory is studied by measuring the memory hysteresis in time. The obtained retention characteristic (35.5% charge loss in 10 years) is due to the large conduction and valence band offsets between the Si-nanoparticles and the Al2O3/HfO2 tunnel oxide. The results show that band engineering is essential in future low-power non-volatile memory devices. In addition, the results show that Si-nanoparticles are promising in memory applications. © The Electrochemical Society

Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via Poole-Frenkel hole emission

A low power zinc-oxide (ZnO) charge trapping memory with embedded silicon (Si) nanoparticles is demonstrated. The charge trapping layer is formed by spin coating 2 nm silicon nanoparticles between Atomic Layer Deposited ZnO steps. The threshold voltage shift (ΔVt) vs. programming voltage is studied with and without the silicon nanoparticles. Applying -1 V for 5 s at the gate of the memory with nanoparticles results in a ΔVt of 3.4 V, and the memory window can be up to 8 V with an excellent retention characteristic (&gt;10 yr). Without nanoparticles, at -1 V programming voltage, the ΔVt is negligible. In order to get ΔVt of 3.4 V without nanoparticles, programming voltage in excess of 10 V is required. The negative voltage on the gate programs the memory indicating that holes are being trapped in the charge trapping layer. In addition, at 1 V the electric field across the 3.6 nm tunnel oxide is calculated to be 0.36 MV/cm, which is too small for significant tunneling. Moreover, the ΔVt vs. electric field across the tunnel oxide shows square root dependence at low fields (E 1 MV/cm) and a square dependence at higher fields (E &gt; 2.7 MV/cm). This indicates that Poole-Frenkel Effect is the main mechanism for holes emission at low fields and Phonon Assisted Tunneling at higher fields. © 2014 AIP Publishing LLC

2-nm laser-synthesized Si nanoparticles for low-power charge trapping memory devices

In this work, the effect of embedding Silicon Nanoparticles (Si-NPs) in ZnO based charge trapping memory devices is studied. Si-NPs are fabricated by laser ablation of a silicon wafer in deionized water followed by sonication and filtration. The active layer of the memory was deposited by Atomic Layer Deposition (ALD) and spin coating technique was used to deliver the Si-NPs across the sample. The nanoparticles provided a good retention of charges (&gt;10 years) in the memory cells and allowed for a large threshold voltage (Vt) shift (3.4 V) at reduced programming voltages (1 V). The addition of ZnO to the charge trapping media enhanced the electric field across the tunnel oxide and allowed for larger memory window at lower operating voltages. © 2014 IEEE

Growth of ∼3-nm ZnO nano-islands using Atomic Layer Deposition

In this work, the deposition of 3-nm dispersed Zinc-Oxide (ZnO) nanislands by thermal Atomic Layer Deposition (ALD) is demonstrated. The physical and electronic properties of the islands are studied using Atomic Force Microscopy, UV-Vis-NIR spectroscopy, and X-ray Photoelectron Spectroscopy. The results show that there is quantum confinement in 1D in the nanoislands which is manifested by the increase of the bandgap and the reduction of the electron affinity of the ZnO islands. The results are promising for the fabrication of future electronic and optoelectronic devices by single ALD step. © 2016 IEEE

∼3-nm ZnO nanoislands deposition and application in charge trapping memory grown by single ALD step

Low-dimensional semiconductor nanostructures are of great interest in high performance electronic and photonic devices. ZnO is considered to be a multifunctional material due to its unique properties with potential in various applications. In this work, 3-nm ZnO nanoislands are deposited by Atomic Layer Deposition (ALD) and the electronic properties are characterized by UV-Vis-NIR Spectrophotometer and X-ray Photoelectron Spectroscopy. The results show that the nanostructures show quantum confinement effects in 1D. Moreover, Metal-Oxide-Semiconductor Capacitor (MOSCAP) charge trapping memory devices with ZnO nanoislands charge storage layer are fabricated by a single ALD step and their performances are analyzed. The devices showed a large memory window at low operating voltages with excellent retention and endurance characteristics due to the additional oxygen vacancies in the nanoislands and the deep barrier for the trapped holes due to the reduction in ZnO electron affinity. The results show that the ZnO nanoislands are promising in future low power memory applications. © The Author(s) 2016

Cubic-phase zirconia nano-island growth using atomic layer deposition and application in low-power charge-trapping nonvolatile-memory devices

The manipulation of matter at the nanoscale enables the generation of properties in a material that would otherwise be challenging or impossible to realize in the bulk state. Here, we demonstrate growth of zirconia nano-islands using atomic layer deposition on different substrate terminations. Transmission electron microscopy and Raman measurements indicate that the nano-islands consist of nano-crystallites of the cubic-crystalline phase, which results in a higher dielectric constant (κ ∼ 35) than the amorphous phase case (κ ∼ 20). X-ray photoelectron spectroscopy measurements show that a deep quantum well is formed in the Al2O3/ZrO2/Al2O3 system, which is substantially different to that in the bulk state of zirconia and is more favorable for memory application. Finally, a memory device with a ZrO2 nano-island charge-trapping layer is fabricated, and a wide memory window of 4.5 V is obtained at a low programming voltage of 5 V due to the large dielectric constant of the islands in addition to excellent endurance and retention characteristics. © 2017 IOP Publishing Ltd