Comparator hysteresis compensation for decision feedback equalisers

High-speed comparators are extensively used in serial link receiver designs. Some comparator architectures can show significant hysteresis that degrade the sensitivity of the receiver, increasing the bit error rate. In this Letter, a comparator hysteresis compensation strategy that re-uses the first tap of a decision feedback equaliser to shift the comparator input voltage, increasing the decision margin is proposed. An updated equaliser coefficient adaptation scheme is also introduced. The proposed technique can be used for binary and multi-level modulations

Vega: A Ten-Core SoC for IoT Endnodes with DNN Acceleration and Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode

The Internet-of-Things (IoT) requires endnodes with ultra-low-power always-on capability for a long battery lifetime, as well as high performance, energy efficiency, and extreme flexibility to deal with complex and fast-evolving near-sensor analytics algorithms (NSAAs). We present Vega, an IoT endnode system on chip (SoC) capable of scaling from a 1.7- μW fully retentive cognitive sleep mode up to 32.2-GOPS (at 49.4 mW) peak performance on NSAAs, including mobile deep neural network (DNN) inference, exploiting 1.6 MB of state-retentive SRAM, and 4 MB of non-volatile magnetoresistive random access memory (MRAM). To meet the performance and flexibility requirements of NSAAs, the SoC features ten RISC-V cores: one core for SoC and IO management and a nine-core cluster supporting multi-precision single instruction multiple data (SIMD) integer and floating-point (FP) computation. Vega achieves the state-of-the-art (SoA)-leading efficiency of 615 GOPS/W on 8-bit INT computation (boosted to 1.3 TOPS/W for 8-bit DNN inference with hardware acceleration). On FP computation, it achieves the SoA-leading efficiency of 79 and 129 GFLOPS/W on 32- and 16-bit FP, respectively. Two programmable machine learning (ML) accelerators boost energy efficiency in cognitive sleep and active states

Confirmation of ovulation from urinary progesterone analysis: assessment of two automated assay platforms

Urinary concentrations of the major progesterone (P4) metabolite pregnanediol-3-glucuronide (PDG) are used to confirm ovulation. We aimed to determine whether automated immunoassay of urinary P4 was as efficacious as PDG to confirm ovulation. Daily urine samples from 20 cycles in 14 healthy women in whom ovulation was dated by ultrasound, and serial weekly samples from 21 women in whom ovulation was unknown were analysed. Daily samples were assayed by two automated P4 immunoassays (Roche Cobas and Abbott Architect) and PDG ELISA. Serial samples were assayed for P4 by Architect and PDG by ELISA. In women with detailed monitoring of ovulation, median (95% CI) luteal phase increase was greatest for PDG, 427% (261–661), 278% (187–354) for P4 Architect and least for P4 Cobas, 146% (130–191), p 0.92). In serial samples classified as (an)ovulatory by PDG, P4 Architect gave ROC AUC 0.95 (95% CI 0.89 to 1.01), with sensitivity and specificity for confirmation of ovulation of 0.90 and 0.91 at a cutoff of 1.67 μmol/mol. Automated P4 may potentially be as efficacious as PDG ELISA but research from a range of clinical settings is required

Preferences across the Menstrual Cycle for Masculinity and Symmetry in Photographs of Male Faces and Bodies

Background: Previous studies have shown that women increase their preference for masculinity during the fertile phase of the menstrual cycle. Evidence for a similar preference shift for symmetry is equivocal. These studies have required participants to choose between subtle variations in computer-generated stimuli, and preferences for more natural stimuli have not been investigated. Methodology/Principal Findings: Our study employed photographs of individual males to investigate women’s preferences for face and body masculinity and symmetry across the menstrual cycle. We collected attractiveness ratings from 25 normally cycling women at high- and low-fertility days of the menstrual cycle. Attractiveness ratings made by these women were correlated with independent ratings of masculinity and symmetry provided by different sets of raters. We found no evidence for any cyclic shift in female preferences. Correlations between attractiveness and masculinity, and attractiveness and symmetry did not differ significantly between high- and low-fertility test sessions. Furthermore, there was no significant difference between high- and low-fertility ratings of attractiveness. Conclusions: These results suggest that a menstrual cycle shift in visual preferences for masculinity and symmetry may be too subtle to influence responses to real faces and bodies, and subsequent mate-choice decisions

On the simulation of fast settling charge pump PLLs up to fourth order

In this paper, we discuss three different models for the simulation of integer-N charge-pump phase-locked loops (PLLs), namely the continuous-time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, output spectral purity analysis methods based upon the time-domain model are introduced and the results are compared with those obtained by means of the s-domain model in terms of phase noise and reference spur estimation. As a case study, we use the three models to analyze a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB-OFDM UWB systems

A CMOS 90 nm 55 mW 3.4-to-9.2 GHz 12 Band frequency synthesizer for MB-OFDM UWB

A frequency synthesizer for UWB MB-OFDM applications is designed in TSMC 90 nm CMOS technology. It is based on two wideband PLLs capable of settling in less than 300 ns with a 66 MHz external reference. The PLL tuning range (6.6–9.2 GHz) is extended down to 3.4 GHz by a dedicated circuit able to divide the output frequency by 1, 1.5 and 2 with a power consumption of less than 3 mW. Measured data fit the UWB MB-OFDM specifications with an integrated phase noise of 2.8° RMS at maximum output frequency and an aggregate spurious tone power of less than 27 dBc. The joint power consumption is 55 mW and the synthesizer core area occupies less than 0.5 mm2

A 0.75-2.2 GHz continuously tunable quadrature VCO

none4A quadrature VCO with +/- 50% tuning continuous tuning range is presented. It is based on a core LC-QVCO with +/- 20% tuning range, a single sideband mixer, two frequency dividers and a multiplexer. The circuit has been implemented in a 0.13 um 1.2 V CMOS technology. The additional area with respect to the core LC-QVCO is 100x100 um. Quadrature error is less than 2°; the phase noise is less than -120 dBc/Hz @ 1 MHz offset over the whole tuning range and is mainly due to the LC-QVCO. Spurs are more than 34 dB below the fundamental in the worst case.mixedD. Guermandi; P. Tortori; E. Franchi Scarselli; A. GnudiD. Guermandi; P. Tortori; E. Franchi Scarselli; A. Gnud