Long range correlations in a 97% excitonic one-dimensional polariton condensate

We report on the realization of an out-of-equilibrium polariton condensate under pulsed excitation in a one-dimensional geometry. We observe macroscopic occupation of a polaritonic mode with only 3% photonic fraction, and a nature strikingly close to that of a bare exciton condensate. With the help of this tiny photonic fraction, the condensate is found to display first-order coherence over distances as large as 10 microns. Based on a driven-dissipative mean field model, we find that the correlations length is limited by the effects of a shallow disorder under non-equilibrium conditions.Comment: 5 pages, 3 figure

A DfT Architecture for Asynchronous Networks-on-Chip

International audienceThe Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these network architectures. To test the SoCs, the main challenge is to reach into the embedded cores (i.e, the IPs). In this case, the DFT techniques that integrate test architectures into the SoCs to ease the test of these SoCs are really favoured. In this paper, we present a new methodology for testing NoC architectures. A modular, generic, scalable and configurable DFT architecture is developed in order to ease the test of NoC architectures. The target of this test architecture is asynchronous NoC architectures that are implemented in GALS systems. The proposed architecture is therefore named ANOC-TEST and is implemented in QDI asynchronous circuits. In addition, this architecture can be used to test the computing resources of the networked SoCs. Some initial results and conclusions are also give

A strange Evans syndrome: a case report

Hepatic angiosarcoma is a rare malignant vascular tumor, which accounts for up to 2% of all primary liver tumors. The most frequent symptoms on presentation are weight loss, weakness and abdominal pain. Diagnosis of diffuse hepatic angiosarcoma can be challenging. We report an original case of diffuse liver angiosarcoma revealed by haematological abnormalities initially diagnosed as an Evans syndrome. Anaemia and thrombocytopenia are rarely the first manifestations of this pathology. They are explained by combination of several mechanisms. Diagnosis of diffuse liver angiosarcoma can be extremely difficult and physicians should be aware of these presentation

How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes

International audienceThe Network-on-Chip (NoC) paradigm is currently known as an alternative solution for the on chip communication in the next SoC generation, especially, asynchronous NoCs. One of the challenges for asynchronous NoC-based systems design is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented

Traitement de la nécrobiose lipoïdique par antipaludéens de synthèse (étude d'une série de 8 cas)

LYON1-BU Santé (693882101) / SudocPARIS-BIUM (751062103) / SudocSudocFranceF

How to Implement an Asynchronous Test Wrapper for Networks-on-Chip Nodes

The Network-on-Chip (NoC) paradigm is currently known as an alternative solution for the on chip communication in the next SoC generation, especially, asynchronous NoCs. One of the challenges for asynchronous NoC-based systems design is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented. 1

Design-for-Test of Asynchronous Networks-on-Chip

International audienceThanks to many advantages, asynchronous circuits have been used to solve the interconnect problems faced by system–on–chip (SoC) designers. Some asynchronous Networks–on–Chip (NoCs) architectures are proposed for the communication within SoCs, but lack of methodology and support formanufacture testing to ensure these communication architectures work correctly. In this paper, we present an innovative asynchronous DFT architecture that allows testing the asynchronous communication network architectures, as well as the synchronous computing resources and the asynchronous/synchronous network interfaces on the asynchronous NoC–based SoCs. This asynchronous DFT architecture is implemented in Quasi Delay Insensitive (QDI) asynchronous circuits and uses an area of about 20 8 Kgates in an asynchronous NoC–based SoC of 4.5 Mgates without memories

Conception en vue du test pour l'architecture d'un réseau sur puce asynchrone

Journées Nationales du Réseau Doctoral en MicroélectroniqueA cause de la complexité de beaucoup d'applications et de l'intégration, les concepteurs embarquent de plus en plus de ressources de calcul (i.e., IPs) dans un système sur puce. Cependant, ceci rend le test de fabrication de ces systèmes plus difficile, notamment pour les systèmes sur puce à base de réseaux sur puce asynchrone. L'objectif de cet article est de proposer d'une architecture DFT (“Design for Test”) innovante pour ces systèmes sur puce. Cette architecture est modulaire, générique, dimensionnable, configurable. Elle est mise en oeuvre en logique asynchrone pour bien s'adapter à la plateforme GALS (Globalement Asynchrone, Localement Synchrone). Quelques premiers résultats et conclusions seront présentés

Conception en vue de Test pour l'Architecture d'un Réseau sur Puce Asynchrone

Journées Nationales du Réseau Doctoral en MicroélectroniqueA cause de la complexit´e de beaucoup d'applications et de l'int´egration, les concepteurs embarquent de plus en plus de ressources de calcul (i.e., IPs) dans un syst`eme sur puce. Cependant, ceci rend le test de fabrication de ces syst`emes plus difficile, notamment pour les syst`emes sur puce `a base de r´eseaux sur puce asynchrone. L'objectif de cet article est de proposer d'une architecture DFT (“Design for Test”) innovante pour ces syst`emes sur puce. Cette architecture est modulaire, g´en´erique, dimensionnable, configurable. Elle est mise en oeuvre en logique asynchrone pour bien s'adapter `a la plateforme GALS (Globalement Asynchrone, Localement Synchrone). Quelques premiers r´esultats et conclusions seront pr´esent´es

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip

9 pagesInternational audienceThe Networks on Chip (NoCs) paradigm has recently emerged as an alternative solution for large complex SoCs' communication. Despite having many attractive attributes, NoCs design has also lots of challenges. One of the challenges is testing network architectures (routers and communication channels) for manufacturing defects, especially, the test of asynchronous NoCs. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable fully asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high throughput Test Access Mechanism (TAM). This paper presents the realization and implementation of this DfT architecture. The validation and experimental results are also presented