A digitally controlled threshold adjustment circuit in a 0.13um SiGe BiCMOS technology for receiving multilevel signals up to 80Gbps

In this paper, a high bandwidth digitally controlled threshold adjustment circuit is proposed which can be used for demodulating high-speed multi-level signals. Simulations of the bandwidth are presented together with measurements of the control currents to indicate the threshold adjustment capability. A bandwidth above 80GHz in a 0.13µm SiGe BiCMOS technology and a threshold tunable between ±160mV in steps of 0.6mV is achieved, allowing very precise control of the threshold level. This allows the circuit to accurately position the threshold on the eye-crossing of a high speed multi-level signals. By applying this circuit to demodulate a duobinary signal over a 40GHz channel, a data rate of up to 80Gbps can be achieved

56+ Gb/s serial transmission using duo-binary signaling

In this paper we present duobinary signaling as an alternative for signaling schemes like PAM4 and Ensemble NRZ that are currently being considered as ways to achieve data rates of 56 Gb/s over copper. At the system level, the design includes a custom transceiver ASIC. The transmitter is capable of equalizing 56 Gb/s non-return to zero (NRZ) signals into a duobinary response at the output of the channel. The receiver includes dedicated hardware to decode the duobinary signal. This transceiver is used to demonstrate error-free transmission for different PCB channel lengths including a state-of-the-art Megtron 6 backplane demonstrator

Analysis and design of a high power, high gain SiGe BiCMOS output stage for Use in a millimeter-wave power amplifier

In this paper a high gain, high power output stage designed in a 250nm SiGe BiCMOS technology is presented. The used topology together with a discussion on the stability of the output stage is explained in detail. In order to increase the gain of the output stage and thus increases the attainable power added efficiency (PAE), positive feedback is used. Furthermore a formula predicting the input impedance of a common base transistor at high frequencies is deducted which explains and predicts the magnitude of the feedback mechanism. The output stage achieves a peak gain of 14.4dB at 31GHz with a maximum output power of 22dBm

DSP-free and real-time NRZ transmission of 50Gb/s over 15km SSMF and 64Gb/s back-to-back with a 1.3um VCSEL

We demonstrate and analyze 50 Gb/s non-return-to-zero (NRZ) transmission over 15 km of standard single-mode fiber (SSMF), 60-Gb/s NRZ transmission over 5 km of SSMF and up to 64-Gb/s NRZ back-to-back using a directly modulated short-cavity long-wavelength single-mode vertical-cavity surface-emitting laser (VCSEL) emitting at 1326 nm. Owing to an analog 6-tap transmit feedforward equalizer, the link can operate without digital signal processing. In all three cases, real-time bit error ratio measurements below the 7% overhead hard-decision forward error correction threshold are demonstrated when transmitting a pseudorandom bit sequence with a period of 2(7) - 1 bits. In addition, we analyze the interplay between the residual fiber chromatic dispersion at the operating wavelength of the VCSEL and the chirp due to direct modulation. These results demonstrate how O-band, short-cavity long-wavelength single-mode VCSELs can be used in intradata center networks, as well as in interdata center networks at reaches below 15 km

Measurements of millimeter wave test structures for high speed chip testing

This paper presents the frequency domain characterization of very high bandwidth connectorized traces and a millimeter wave rat race coupler. These connectorized differential grounded coplanar waveguide traces, essential for the testability of high speed integrated circuits, have a measured flat frequency response up to 67GHz which indicates correct connector footprint and transmission line design. The differential traces narrow down to a chip scale pitch of 150 μm allowing direct flip chip connections. This enabling the testing of millimeter wave integrated circuits without the need for probing. Furthermore, a 50GHz rat race coupler was fabricated to generate a differential clock from a single ended clock source

25Gb/s 3-level burst-mode receiver for high serial rate TDM-PONs

We report the first 25Gb/s 3-level modulated BM-RX employing a ¼-rate linear BM APD-TIA and a custom decoder IC. We successfully demonstrated burst-mode sensitivity of -20.4dBm with 18dB dynamic burst-to-burst for 25Gb/s upstream links

Adaptive transmit-side equalization for serial electrical interconnects at 100 Gb/s using duobinary

The ever-increasing demand for more efficient data communication calls for new, advanced techniques for high speed serial communication. Although newly developed systems are setting records, off-line determination of the optimal equalizer settings is often needed. Well-known adaptive algorithms are mainly applied for receive-side equalization. However, transmit-side equalization is desirable for its reduced linearity requirements. In this paper, an adaptive sign-sign least mean square equalizer algorithm is developed applicable for an analog transmit-side feed-forward equalizer (FFE) capable of transforming non-return-to-zero modulation to duobinary (DB) modulation at the output of the channel. In addition to the derivation of the update strategy, extra algorithms are developed to cope with the difficult transmit-receive synchronization. Using an analog six tap bit-spaced equalizer, the algorithm is capable of optimizing DB communication of 100Gb/s over 1.5-m Twin-Ax cable. Both simulations and experimental results are presented to prove the capabilities of the algorithm demonstrating automated determination of FFE parameters, such that error-free communication is obtained (BER<10(-13) using PRBS9)