774 research outputs found

    Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

    Get PDF
    An apparatus is disclosed which includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a dc magnetron sputtering system. A gas inlet introduces various gases to the vacuum chamber and creates various gas plasma during the sputtering steps. The rotating turntables insure that the respective wafers are present under the sputtering guns for an average amount of time such that consistency in sputtering and deposition is achieved. By continuous and sequential processing of the wafers in a common vacuum chamber without removal, the adverse affects of exposure to atmospheric conditions are eliminated providing higher quality circuit contacts and functional device

    Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

    Get PDF
    The processing of wafer devices to form multilevel interconnects for microelectronic circuits is described. The method is directed to performing the sequential steps of etching the via, removing the photo resist pattern, back sputtering the entire wafer surface and depositing the next layer of interconnect material under common vacuum conditions without exposure to atmospheric conditions. Apparatus for performing the method includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a DC magnetron sputtering system. A gas inlet is provided in the chamber for the introduction of various gases to the vacuum chamber and the creation of various gas plasma during the sputtering steps

    Method of construction of a multi-cell solar array

    Get PDF
    The method of constructing a high voltage, low power, multicell solar array is described. A solar cell base region is formed in a substrate such as but not limited to silicon or sapphire. A protective coating is applied on the base and a patterned etching of the coating and base forms discrete base regions. A semiconductive junction and upper active region are formed in each base region, and defined by photolithography. Thus, discrete cells which are interconnected by metallic electrodes are formed

    Multilevel metallization method for fabricating a metal oxide semiconductor device

    Get PDF
    An improved method is described of constructing a metal oxide semiconductor device having multiple layers of metal deposited by dc magnetron sputtering at low dc voltages and low substrate temperatures. The method provides multilevel interconnections and cross over between individual circuit elements in integrated circuits without significantly reducing the reliability or seriously affecting the yield

    High and low threshold P-channel metal oxide semiconductor process and description of microelectronics facility

    Get PDF
    The fabrication techniques and detail procedures for creating P-channel Metal-Oxide-Semiconductor (P-MOS) integrated circuits at George C. Marshall Space Flight Center (MSFC) are described. Examples of P-MOS integrated circuits fabricated at MSFC together with functional descriptions of each are given. Typical electrical characteristics of high and low threshold P-MOS discrete devices under given conditions are provided. A general description of MSFC design, mask making, packaging, and testing procedures is included. The capabilities described in this report are being utilized in: (1) research and development of new technology, (2) education of individuals in the various disciplines and technologies of the field of microelectronics, and (3) fabrication of many types of specially designed integrated circuits which are not commercially feasible in small quantities for in-house research and development programs

    Electrophoretic Analysis of the Proteins of Body Fluids in Various Disease States

    Get PDF
    Plasma, serum, and body fluid specimens (pleural fluid, ascitic fluid, synovial fluid, edema fluid, hydrocele fluid, cyst fluid, lymph, bile, and subdural fluid) from patients with heart disease, carcinoma, liver disease, and arthritis, were subjected to electrophoretic analysis. A decrease in plasma albumin and an increase in globulin components occurred in the disease conditions. In most instances the albumin and gamma globulin were higher, the α1 globulin the same, and the α2 and β globulin and fibrinogen in lower concentration in the fluid than in the corresponding plasma specimen. The distribution of the protein components between the plasma and fluid is explained on the basis of their molecular weights

    Electrophoretic Studies of the Proteins of Plasma and Ascitic Fluid in Cirrhosis

    Get PDF
    A series of plasma and ascitic fluid specimens withdrawn from patients with cirrhosis, and a series from one patient over a seven-week period prior to his death, were subjected to electrophoretic analysis. The results indicate a qualitative similarity between plasma and ascitic fluid protein patterns. In most instances, the ascitic fluid contained more albumin, alpha1 and gamma globulins than the plasma, whereas the plasma was richer in alpha2 and beta globulins and fibrinogen. Based on the molecular weights of the protein fractions, the values indicate that selective protein enrichment of ascitic fluid may be related to the molecular size of the protein components

    The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

    Get PDF
    The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included
    corecore