The method of constructing a high voltage, low power, multicell solar array is described. A solar cell base region is formed in a substrate such as but not limited to silicon or sapphire. A protective coating is applied on the base and a patterned etching of the coating and base forms discrete base regions. A semiconductive junction and upper active region are formed in each base region, and defined by photolithography. Thus, discrete cells which are interconnected by metallic electrodes are formed

Feltner, W. R.

Hollis, B. R., Jr.

Routh, D. E.

English

NASA Technical Reports Server

United States Patent 4,156,309 
Routh et ai. [45] May 29, 6979 
[54] METHOD OF CONSTRUCTION OF A 
MULTI-CELL SOLAR ARRAY 
1561 References Cited 
U.S. PATENT DOCUMENTS 
[75] Inventors: 
[73] Assignee: 
[21] Appl. No.: 
[22] Filed: 
3,471,923 10/1969 Lamorte ................................. 29/573 
Donald E. Routh; Ben R. HOW, 3,912,556 10/1975 Grenon .................................. 29/572 
William R. Feltner. all of Huntsville, 3,999,205 12/1976 Stewart .................................. 357/45 . .  
Ala. . 4,045,245 8/1977 Coleman ................................ 29/572 
The United States of America as 
represented by the Administrator of 
the National Aeronautics and Space 
Administration, Washington, D.C. 
863,773 
Dec. 23,1977 
Primary Examiner-W. Topman 
Attorney, Agent, or Firm-George J. Porter; John R. 
Manning; L. D. Wofford, Jr. 
ABSTRACT 1571 
The method of constructing a high voltage, low power, 
multi-cell solar array wherein a solar cell base region is 
formed in a substrate such as but not limited to that of 
silicon or on a substrate of sapphire, and then by the 
steps of application of a protective coating on the base, 
patterned etching of the coating and base to thereby 
form discrete base regions, forming a semi-conductive 
[51] Int. Cl.2 .............................................. BOlJ 17/00 
[52] u.S. Cl. ................................... 29/572; 29/577 C; 
29/578; 29/580; 357/45 
[58] Field of Search ................. 29/572, 573, 577, 578, 
29/580; 351/45 
junction and upper active region in each base region 
defined by photolithography, and thus forming discrete 
cells which are interconnected by metallic electrodes. 
5 Claims, 8 Drawing Figures 
https://ntrs.nasa.gov/search.jsp?R=19790018304 2020-03-20T19:17:11+00:00Z
U.S. Patent 
- IO 
FIG. I 
F I G .  2 
F I G .  3 
F I G .  4 
'12 
FIG.  5 
F I G .  6 
FIG.  7 
F I G .  0 
May 29, 1979 4,156,309 
- IOI 
-- 21 22 28 
f 12 
122 12b IO 12/c I 2'd - 
I I 
360 38a 36.b 3 8 b  3 6 c  38c 3 6 d  
I 30 a' 306 3 6 c  - 
4,156,309 
1 
METHOD OF CONSTRUCMON OF A 
MULTI-CELL SOLAR ARRAY 
ORIGIN OF THE INVENTION 
The invention described herein was made by employ- 
ees of the United States Government, and may be manu- 
factured and used by or for the Government of the 
United States for governmental purposes without the 
BACKGROUND OF THE INVENTION 
5 
payment of any royalties thereon or therefor. 10 
1. Field of the Invention 
This invention relates to the method of construction 
of photovoltaic devices, and particularly to a method of 15 
construction of multi-cell photovoltaic devices, or solar 
arrays as they are commonly referred to. 
2. General Description of the Prior Art 
Heretofore, the usual method of obtaining higher 
than single cell voltages from solar arrays has been fust 20 
to construct physically separate solar cells and then to 
simply wire them together. Alternately, it has been 
proposed that multi-cell solar arrays be constructed on 
a single insulating substrate and, by a method which 
includes the initial deposition of electrical connections 25 
on the substrate, form successive, opposite polarity, or 
doped, states, semi-conductive layers. 
The interconnection of individual solar cells typically 
requires a skilled technician which is both time consum- 
ing and expensive, and the interconnections are typi- 30 
c d y  not as reliable as the individual cells, and thus 
maximum utilization of the cells is not obtained. 
A problem to be anticipated with the construction of 
proposed devices utilizing an insulating substrate is that 
of low light-to-electrical energy conversion efficiency. 35 
It is an object of this invention to provide a method of 
manufacture which overcomes the aforesaid difficulties. 
SUMMARY OF THE INVENTION 
effect on a substrate of silicon or sapphire a semi-con- 
ductive layer with an appropriate impurity concentra- 
tion to effect a semi-conductive base region. Alter- 
nately, the substrate may be of a different material, 
provided the crystal lattice structure is substantially 45 
similar to that of this layer. Next, by photolithography, 
the base region is divided into a plurality of base re- 
gions, and as separated, upper active surface regions are 
created in the base regions by diffusion of an impurity of 
In accordance with this invention, the first step is to 40 
Next, as shown in FIG. 2, a semi-conductive base 
region 12 is formed by the diffusion of an impurity 
concentration of approximately 1017 atoms/cm3 into a 
silicon substrate wherein the impurity type is opposite 
to the impurity type of the substrate. Diffusion is to a 
depth of 7 to 10 micrometers. In the case of a sapphire 
substrate, an epitaxy layer of silicon is deposited to a 
thickness of 7 to 10 micrometers on the substrate, hav- 
ing an impurity concentration of approximately 1017 
atoms/cm’ in this layer. 
Next, and with reference to FIG. 3, there is grown or 
deposited a protective dielectric layer 14, being of a 
material such as silicon dioxide. The layer would be 
effected to an approximate depth or thickness of 300 
micrometers. On it there is applied a layer of photo 
resist, and by photolithography, a pattern of photo resist 
16 is formed to define solar cell locations l8a-18d sepa- 
rated by exposed boundary regions 20. 
Next, as shown in PIG. 4, exposed protective dielec- 
tric layer 14 in the boundary regions is etched away by 
using a dielectric etch such as a room temperature 
buffer etch H2O:HFNH4F to etch silicon dioxide. 
After this, the photo resist 16 in solar cell locations 
18a-18d is removed. Next, the exposed areas of base 12 
are etched away using a preferential silicon etch such as 
H20:KOH. This etch subdivides base region 12 into 
isolated solar cell base regions 12u, 12b, 12,  and 13d 
and also slopes walls 18 to the base regions for good 
metallic coverage as shown in FIG. 8. 
Next, as shown in FIG. 5, a second protective dielec- 
tric coating is grown over the entire wafer to a depth of 
300 micrometers. On top of it, photo resist is applied 
and processed to leave a pattern of photo resist cover 
regions 22, 24, 26, and 28. Between these regions, por- 
tions of protective dielectric cover 21, not covered by 
the photo resist, are etched away (FIG. 6) by a dielec- 
tric etch. The photo resist covering regions 22, 24, 26, 
and 28 is dissolved and removed. In the etched regions, 
regions 3Oa30d solar cell junctions are created by dif- 
fusing into the now isolated bases 12u-12d an opposite 
polarity type impurity (to that initially used in creating 
base 12), diffusion being to a depth of 0.25 to 0.5 mi- 
crometers and of a concentration of approximately 1020 
atoms/cm3. In this way, discrete solar cells 31a31d are 
formed, having upper active surfaces 32u-326. 
Next, as illustrated in FIG. 6, the remaining portion 
of protective dielectric coating 21 is etched away with 
dielectric etch. After this, as shown in FIG. 7, a new 
opposite polarity tothat employed in the cr&tion of 50 protective dielectric coating 34 is formed over the en- 
base regions. By photolithography and etching, metal tUe Surface, which Coating would be Of a thickness of 
contacts are formed which interconnect between the 100 to 300 micrometers and embodying an outer surface 
uppep active region of one cell and the lower base re- Of blue or purple to serve as an anti-reflection coating 
@on ofthe adjoining cell. In this manner, the cells are so for S o h  cells 31a-31d. Assuming that the protective 
connected in series as to m&e their voltages additive. 55 dielectric coating shown does not provide the anti- 
reflective feature, then at this point a separate anti- 
reflection material should be added to the upper surface 
of solar cells 31a31d. 
Next, and with reference to FIG. 7, cell cover photo 
60 resist regions 36a-36d and electrode cover photo resist 
regions 38a-38c are formed on the surface of protective 
dielectric coating 34, and thereafter that portion not 
covered by the photo resist is etched away, enabling, as 
Referring to FIG. 1, a wafer of microelectronic grade shown in FIG. 8, electrodes 40a-40e to be formed. As a 
silicon or sapphire is cleaned and employed to form a 65 means of forming electrodes, a metallic coating, such as 
substrate 10. Where silicon is used, the silicon should aluminum, is applied over the entire surface of the de- 
have a high resistivity, that is, a resistivity of 100 ohms vice and then covered by photo resist which is pro- 
cm or greater. cessed to protect desired electrode areas. The balance 
BRIEF DE!XRIFTION OF THE 
FIGS. 1-8 illustrate the progressive steps in the for- 
mation of a solar array as contemplated by this inven- 
tion. 
DETAILED DESCRIPTION OF THE 
DRAWINGS 
4,156,w? 
3 4 
of unprotected metallic coating is then etched away and polarity to that of said first layer, whereby a semi- 
finally the photo resist dissolved and removed. conductive junction is formed between layers; 
Electrode 40a connects to base 12a of solar cell 31u, forming a protective insulative coating over a portion 
and electrode 40b connects between active region 32u of the top surface of each said second layer of each 
of that solar cell and base 126 of solar cell 31b. Elec- 5 section which extends on one side to cover an edge 
trode 4Oc similarly connects between the active region portion of said first layer of that section and leaves 
of solar cell 316 and base 12c of solar cell 31c. Electrode uncoated an opposite edge portion of the first layer 
40d connects between active region 3 2  of solar cell 31c of that section; and 
and base 12d of solar cell 31d. Electrode 40e connects to forming electrical connections between adjoining 
the active region of solar cell 31d and it, together with 10 said sections, connection being between an un- 
electrode 404 provides output terminals across which coated portion of a first layer of one section and an 
the full series voltage of the solar cells is obtained. uncoated portion of a second layer of an adjoining 
It is to be appreciated that by the method described, said section, said uncoated portions being those left 
a solar array may be created which is monolithic and uncoated from the preceding step. 
which thereby eliminates the need to individually con- 15 2. The method as set forth in claim 1 wherein said 
nect cells. By forming the solar cells by diffusion into a 
substrate of silicon, or applying an epitaxy layer of the forming of a photo resist over said first layer 
silicon over an insulating substrate, and therefrom form- other than over desired said boundary paths; 
ing a semi-conductor junction, the efficiency of stan- etching away said protective dielectric coating and 
dard discrete solar cells is retained. said first layer of said semi-conductive material in 
Having thus described our invention, what is claimed regions corresponding to said boundary paths; and 
is: removing said photo resist. 
1. The method of making a multi-cell solar array 3. The method as set forth in claim 2 wherein said 
comprising: material is silicon containing an impurity providing a 
forming on a substrate a first layer of semi-conductive 25 second conductivity type, and said material having a 
resistivity of at least 100 ohms. cm. 
4. The method as set forth in claim 2 wherein said 
substrate is of sapphire, and said first layer is formed by 
applying to said substrate an epitaxy layer of silicon to 
30 a thickness of 7 to 10 micrometers, and said fust layer 
having an impurity concentration of approximately 
1017 atoms/cm3. 
5. The method as set forth in claim 2 wherein said 
removal of protective dielectric along said boundary 
removing the balance of said protective dielectric 35 paths is by a dielectric etch, and the removal of said first 
layer in said boundary paths is etched by a preferential 
silicon etch. 
step of removing along boundary paths comprises: 
20 
material of a first conductivity type, said substrate 
being of a material which has a crystal lattice struc- 
ture substantially similar to that of said layer; 
forming a protective dielectric coating over said 
layer of semi-conductive material; 
removing, along boundary paths, said protective di- 
electric coating and semi-conductive material, and 
thereby separating discrete sections of said semi- 
conductive material; 
coating and forming in central top regions of said 
sections a second semi-conductive layer of smaller 
top surface than said first layer and of opposite * * * * *  
50 
55 
60 
65 


Method of construction of a multi-cell solar array

Abstract

Similar works

Full text

Available Versions

NASA Technical Reports Server