A partial order semantics approach to the clock explosion problem of timed automata

AbstractWe present a new approach to the symbolic model checking of timed automata based on a partial order semantics. It relies on event zones that use vectors of event occurrences instead of clock zones that use vectors of clock values grouped in polyhedral clock constraints. We provide a description of the different congruences that arise when we consider an independence relation in a timed framework. We introduce a new abstraction, called catchup equivalence which is defined on event zones and which can be seen as an implementation of one of the (more abstract) previous congruences. This formal language approach helps clarifying what the issues are and which properties abstractions should have. The catchup equivalence yields an algorithm to check emptiness which has the same complexity bound in the worst case as the algorithm to test emptiness in the classical semantics of timed automata. Our approach works for the class of timed automata proposed by Alur–Dill, except for state invariants (an extension including state invariants is discussed informally). First experiments show that the approach is promising and may yield very significant improvements

A Low Power Multi-Channel Single Ramp ADC With Up to 3.2 GHz Virtual Clock

During the last decade, ADCs using single ramp architecture have been widely used in integrated circuits dedicated to nuclear science applications. These types of converters are actually very well suited for low power, multi-channel applications. Moreover their wide dynamic range and their very good differential non-linearity are perfectly matched to spectroscopy measurement. Unfortunately, their use is limited by their long conversion time, itself limited by their maximum clock frequency. A new architecture is described in this paper. It permits speeding up the conversion time of the traditional ramp ADC structures by a factor of 32 while keeping a low power consumption. Measurement results on a 4-channel, 12-bit prototype using a 3.2 GHz virtual clock are then presented in detail, showing excellent performances of linearity and noise

CARET analysis of multithreaded programs

Dynamic Pushdown Networks (DPNs) are a natural model for multithreaded programs with (recursive) procedure calls and thread creation. On the other hand, CARET is a temporal logic that allows to write linear temporal formulas while taking into account the matching between calls and returns. We consider in this paper the model-checking problem of DPNs against CARET formulas. We show that this problem can be effectively solved by a reduction to the emptiness problem of B\"uchi Dynamic Pushdown Systems. We then show that CARET model checking is also decidable for DPNs communicating with locks. Our results can, in particular, be used for the detection of concurrent malware.Comment: Pre-proceedings paper presented at the 27th International Symposium on Logic-Based Program Synthesis and Transformation (LOPSTR 2017), Namur, Belgium, 10-12 October 2017 (arXiv:1708.07854

Convex Hull of Arithmetic Automata

Arithmetic automata recognize infinite words of digits denoting decompositions of real and integer vectors. These automata are known expressive and efficient enough to represent the whole set of solutions of complex linear constraints combining both integral and real variables. In this paper, the closed convex hull of arithmetic automata is proved rational polyhedral. Moreover an algorithm computing the linear constraints defining these convex set is provided. Such an algorithm is useful for effectively extracting geometrical properties of the whole set of solutions of complex constraints symbolically represented by arithmetic automata

Development of a modular CdTe detector plane for gamma-ray burst detection below 100 keV

We report on the development of an innovative CdTe detector plane (DPIX) optimized for the detection and localization of gamma-ray bursts in the X-ray band (below 100 keV). DPIX is part of an R&D program funded by the French Space Agency (CNES). DPIX builds upon the heritage of the ISGRI instrument, currently operating with great success on the ESA INTEGRAL mission. DPIX is an assembly of 200 elementary modules (XRDPIX) equipped with 32 CdTe Schottky detectors (4x4 mm2, 1 mm thickness) produced by ACRORAD Co. LTD. in Japan. These detectors offer good energy response up to 100 keV. Each XRDPIX is readout by the very low noise front-end electronics chip IDeF-X, currently under development at CEA/DSM/DAPNIA. In this paper, we describe the design of XRDPIX, the main features of the IDeF-X chip, and will present preliminary results of the reading out of one CdTe Schottky detector by the IDeF-X V1.0 chip. A low-energy threshold around 2.7 keV has been measured. This is to be compared with the 12-15 keV threshold of the ISGRI-INTEGRAL and BAT-SWIFT instruments, which both use similar detector material.Comment: 5 pages, 4 figures in color, Advances in Space Research, COSPAR meeting, Beijing (2006

MUNCH - Automated Reasoner for Sets and Multisets

This system description provides an overview of the MUNCH reasoner for sets and multisets. MUNCH takes as the input a formula in a logic that supports expressions about sets, multisets, and integers. Constraints over collections and integers are connected using the cardinality operator. Our logic is a fragment of logics of popular interactive theorem provers, and MUNCH is the first fully automated reasoner for this logic. MUNCH reduces input formulas to equisatisfiable linear integer arithmetic formulas. MUNCH reasoner is publicly available. It is implemented in the Scala programming language and currently uses the SMT solver Z3 to solve the generated integer linear arithmetic constraints

Constrained Dynamic Tree Networks

We generalise Constrained Dynamic Pushdown Networks, introduced by Bouajjani\et al, to Constrained Dynamic Tree Networks.<br>In this model, we have trees of processes which may monitor their children.<br>We allow the processes to be defined by any computation model for which the alternating reachability problem is decidable.<br>We address the problem of symbolic reachability analysis for this model. More precisely, we consider the problem of computing an effective representation of their reachability<br>sets using finite state automata. <div>We show that backwards reachability sets starting from regular sets of configurations are always regular. </div><div>We provide an algorithm for computing backwards reachability sets using tree automata.<br><br></div