Energy-efficient wideband transceiver with per-band equalisation and synchronisation

To emit in the TV white space (TVWS) spectrum, the regulator has requested very strict spectral masks, which can be fulfilled using a FFT-modulated filter-bank multi-carrier system (FBMC) to extract one or several TVWS channels in the 470--790MHz range. Such a system reduces the channel dispersion, but even with near-perfectly reconstructing filter bank, the need for equalisation and synchronisation remains. In this work, we propose a per-band equalisation and synchronisation approach, performed by a constant modulus algorithms running concurrently with a direction-directed adaptation process for faster convergence and reduced phase ambiguity. We compare symbol- and fractionally-spaced versions, and investigate their fixed-point implementation on an FPGA. We compare the performance of the different systems in terms of mean squared error, computational cost, and robustness towards noise

Dynamic spectrum access : secondary user coexistence in the FM band

The explosion of wireless everything in recent years has placed a strain on the radio spectrum, and has led to the so-called ‘spectrum crunch’, where the spectrum is described as being nearly at capacity [1]. It is widely accepted that in reality this is not the case, as great numbers of ‘allocated’ bands are underutilized or not in use at all. In other words, the radio spectrum is not used as efficiently as it could be. Commonly, bands (containing many channels) are classified by spectrum regulators for a particular type of use, such as those for FM Radio, Digital TV and cellular services. If there are not enough Primary Users (PUs) to use all of the channels in these bands, they lie empty. Using new spectrum access techniques, these channels can be targeted for 5G and IoT applications. This work focuses on targeting the FM Radio band (88-108 MHz). Signals broadcast at these frequencies have excellent propagation characteristics, and are able to diffract around objects such as hills and human-made structures, and penetrate through buildings well. Recent studies [2] have shown that a significant portion of the 100 individual 200 kHz-wide FM Radio channels are unused at any given location

High-level synthesis for medical image processing on Systems on Chip : a case study

Adaptive radiotherapy is a technique intended to increase the accuracy of radiotherapy. Currently, it is not clinically feasible due to the time required to process the images of patient anatomy. Hardware acceleration of image processing algorithms may allow them to be carried out in a clinically acceptable timeframe. This paper presents the experiences encountered using high-level synthesis tools to design an accelerated segmentation algorithm for computed tomography images targeted for implementation on a System on Chip. Hardware coprocessors and their interfaces for optimal threshold generation and 3D mean filter algorithms were synthesised from C++ functions. Hardware acceleration significantly outperformed the software only implementation. The high-level synthesis tools allowed the rapid exploration of different design options. However, hardware design knowledge was still necessary in order to interpret the results effectively

Rapid prototyping and validation of FS-FBMC dynamic spectrum radio with simulink and ZynqSDR

This paper presents the research carried out in developing and targeting a novel real-time Dynamic Spectrum Access (DSA) Frequency Spread Filter Bank Multicarrier (FS-FBMC) transmitter prototype to programmable ‘ZynqSDR’ Software Defined Radio (SDR) hardware, and introduces a series of experiments used to validate the design’s ‘cognitive’ DSA capabilities. This transmitter is a proof of concept, that uses DSA techniques to enable Secondary Users (SUs) to access the band traditionally used for FM Radio broadcasting (88-108 MHz), and establish data communication channels in vacant parts of the FM Radio Primary User (PU) spectrum using a multicarrier modulation scheme with a Non Contiguous (NC) channel mask. Once implemented on the hardware, the transmitter is subjected to various FM Radio environments sampled from around Central Scotland, and it is demonstrated that it can dynamically adapt its NC transmitter mask in real time to protect the FM Radio signals it detects. A video is presented of this dynamic on-hardware spectral reconfiguration, and the reader is encouraged to view the video to appreciate the responsiveness of the design. An investigation into potential FBMC guardband sizes is carried out, with initial findings indicating a guardband of 200 kHz (either side of an FM Radio station) is required in order to prevent interference with the PUs. This paper also demonstrates the capabilities of the MATLAB®/ Simulink ZynqSDR workflow, and provides a case study and reference design that we feel other researchers working in this field can benefit from

FPGA implementation of a memory-efficient Hough Parameter Space for the detection of lines

The Line Hough Transform (LHT) is a robust and accurate line detection algorithm, useful for applications such as lane detection in Advanced Driver Assistance Systems. For real-time implementation, the LHT is demanding in terms of computation and memory, and hence Field Programmable Gate Arrays (FPGAs) are often deployed. However, many small FPGAs are incapable of implementing the LHT due to the large memory requirement of the Hough Parameter Space (HPS). This paper presents a memory-efficient architecture of the LHT named the Angular Regions - Line Hough Transform (AR-LHT). We present a suitable FPGA implementation of the AR-LHT and provide a performance and resource analysis after targeting a Xilinx xc7z010-1 device. Results demonstrate that, for an image of 1024x1024 pixels, approximately 48% less memory is used than the Standard LHT. The FPGA architecture is capable of processing a single image in 9.03ms

Streaming Convolutional Neural Network FPGA architecture for RFSoC data converters

This paper presents a novel Convolutional Neural Network (CNN) FPGA architecture designed to perform processing of radio data in a streaming manner without interruption. The proposed architecture is evaluated for radio modulation classification tasks implemented on an AMD RFSoC 2x2 development board and operating in real-time. The proposed architecture leverages optimisation such as the General Matrix-to-Matrix (GEMM) transform, on-chip weights, fixed-point arithmetic, and efficient utilisation of FPGA resources to achieve constant processing of a stream of samples. The performance of the proposed architecture is demonstrated through accuracy results obtained during live modulation classification, while operating at a sampling frequency of 128 MHz before decimation. The proposed architecture demonstrates promising results for real-time, time-critical CNN applications

Ultra-wideband SDR architecture for AMD RFSoCs and PYNQ based GNU Radio blocks

The AMD RFSoC (Radio Frequency System on Chip) architecture has gained significant attention within the Software Defined Radio (SDR) community for its integration of Radio Frequency (RF) frontend, FPGA fabric and Linux-capable Arm-based processing system in a single package. Despite its accessibility to researchers via the RFSoC 2x2 and RFSoC 4x2 development board platforms, its adoption within the GNU Radio community has been limited. This work demonstrates the potential of combining RFSoC with GNU Radio by utilizing a bidirectional QSFP network link to transmit and receive a wideband Orthogonal Frequency-Division Multiplexing (OFDM) signal. Using the remote procedure calls we are able to control the Tx/Rx center frequency and RFSoCs Digital Up/Down Converter (DUC/DDC) rates from the host PC to achieve runtime configurable bandwidth. Additional signal inspection and visualisation is implemented using existing GNU Radio GUI widgets and analysis blocks

On applications of dependent types to parameterised digital signal processing circuits

We explore the use of dependent types to address the disparity between the theory and the practical hardware description of DSP circuits. After discussing an approach to modeling synchronous circuit behaviour in Idris (a pure functional language with dependent types), two DSP case studies are introduced — an FIR filter with optimal wordlengths and a CIC decimator with register pruning. Both of these scenarios prove difficult to describe in a parameterised fashion using traditional HDLs and, as such, many implementations rely on ad hoc circuit generators which are challenging to test and evaluate. This work demonstrates that such circuits are readily described in an environment with dependent types. Dependent types can also encode various contracts between the IP designer and its user. These contracts are automatically verified by the Idris type checker before compilation, precluding many common mistakes in IP development and evaluation

RFSoC implementation of runtime reconfigurable numerologies for 5G New Radio

The 5G New Radio (5G NR) mobile standard provides considerable bandwidth and latency advantages compared to its predecessor, 4th Generation Long Term Evolution (4G LTE). The 5G NR standard defines flexible numerologies, giving variable Cyclic Prefix Orthogonal Frequency Division Multiplexing (CP-OFDM) subcarrier spacing and cyclic prefix options. This work proposes a Radio Frequency System on Chip (RFSoC) single chip transmitter solution with runtime reconfigurable numerology, simulating a deployable Radio Unit (RU) which could support both sub-6 GHz and mmWave 5G NR transmission

Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH

We present a new low-cost, high-speed parallel FIR filter generator targeting the Xilinx Radio Frequency System on Chip (RFSoC) and direct RF sampling applications. We compose two existing approaches in a novel hierarchy: efficient parallelism with Fast FIR Algorithm (FFA) structures, and efficient multiplierless FIR implementations with Hcub. The resource usage advantages (in both area and type) are compared with similar output from the traditional architecture, exemplified by vendor tools, as well as the Hcub-based filters without the FFA optimisation. Although these techniques are well studied individually in the literature, they have not enjoyed mainstream use as their structural complexity proves awkward to capture with traditional Hardware Description Languages (HDLs). This work continues a discussion of the use of functional programming techniques in hardware description, highlighting the benefits of having easily composable circuit generators