An Analysis of Global High Technology Leadership and the Role of Governmental Incentives

The United States has long been considered a pioneer in emerging technologies. But there is an abundance of literature to document that other nations are catching up and that developing nations adopt advanced technologies by leapfrogging state of the art technology platforms. Countries such as Japan, Korea and more recently China, have emerged as contenders for technology leadership in various areas. In this paper, we first analyze the literature to identify the key factors that determine global technology leadership. Based on the literature, we develop a model to analyze the relationship between these factors and technology leadership. In addition, we propose that government support, such as incentives and expenditure on R&D etc., impact this relationship and strengthen it. We use panel data analysis to test this relationship and our findings indicate that R&D and main science and technology indicators (MSTI) are significant determinants of technology leadership. This work presents several implications and a path forward for global technology leadership

Consumerization of IT: Risk Mitigation Strategies and Good Practices. Responding to the Emerging Threat Environment.

This report presents security policies that can be deployed to mitigate risks that are related with the trend of Consumerization of IT (COIT) and Bring Your Own Device (BYOD). The aim of this document is to identify mitigation strategies, policies and controls for the risks identified in this area

Project IP-3 Improved cassava for the developing world Annual Report 2002

It has been challenging for the technical and regulatory communities to formulate requirements for trustworthiness of the cyber-physical systems (CPS) due to the complexity of the issues associated with their design, deployment, and operations. The US National Institute of Standards and Technology (NIST), through a public working group, has released a CPS Framework that adopts a broad and integrated view of CPS and positions trustworthiness among other aspects of CPS. This paper takes the model created by the CPS Framework and its further developments one step further, by applying ontological approaches and reasoning techniques in order to achieve greater understanding of CPS. The example analyzed in the paper demonstrates the enrichment of the original CPS model obtained through ontology and reasoning and its ability to deliver additional insights to the developers and operators of CPS.Comment: IET PETRAS 2018 conferenc

Gate-Level Information Flow Tracking for Security Lattices

High-assurance systems found in safety-critical infrastructures are facing steadily increasing cyber threats. These critical systems require rigorous guarantees in information flow security to prevent confidential information from leaking to an unclassified domain and the root of trust from being violated by an untrusted party. To enforce bit-tight information flow control, gate-level information flow tracking (GLIFT) has recently been proposed to precisely measure and manage all digital information flows in the underlying hardware, including implicit flows through hardware-specific timing channels. However, existing work in this realm either restricts to two-level security labels or essentially targets two-input primitive gates and several simple multilevel security lattices. This article provides a general way to expand the GLIFT method for multilevel security. Specifically, it formalizes tracking logic for an arbitrary Boolean gate under finite security lattices, presents a precise tracking logic generation method for eliminating false positives in GLIFT logic created in a constructive manner, and illustrates application scenarios of GLIFT for enforcing multilevel information flow security. Experimental results show various trade-offs in precision and performance of GLIFT logic created using different methods. It also reveals the area and performance overheads that should be expected when expanding GLIFT for multilevel security

Evaluation of a PUF Device Authentication Scheme on a Discrete 0.13um SRAM

status: accepte