Study of electron traps associated with oxygen superlattices in n‐type silicon

status: publishe

Hf-based high-k dielectrics for p-Ge MOS gate stacks

The physical and electrical properties of the gate stack high-k/Al2O3/GeO2/p-Ge were studied in detail, where the high-k is either HfO2 or alloyed HfO2 (HfZrOy, HfGdOx, or HfAlOx). Electrical measurements combined with x-ray photoelectron spectroscopy chemical bonding analysis and band alignment determination were conducted in order to assess the suitability of hafnium-based high-k for this kind of gate stacks, with emphasis on low density of interface states and border traps. HfAlOx was found to be the most promising high-k from those studied. The authors have also found that the current- voltage trends for the various systems studied can be explained by the band alignment of the samples obtained by our x-ray photoelectron spectroscopy analysis.Fil: Fadida, Sivan. Technion - Israel Institute of Technology; IsraelFil: Palumbo, Félix Roberto Mario. Technion - Israel Institute of Technology; Israel. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Nyns, Laura. Imec; BélgicaFil: Lin, Dennis. Imec; BélgicaFil: Van Elshocht, Sven. Imec; BélgicaFil: Caymax, Matty. Imec; BélgicaFil: Eizenberg, Moshe. Technion - Israel Institute of Technology; Israe

Low-temperature epitaxy of highly-doped n-type Si at high growth rate by chemical vapor deposition for bipolar transistor application

peer reviewedWe investigated the growth of in-situ n-type doped epitaxial Si layers with arsenic and phosphorus by means of low-temperature chemical vapor deposition using trisilane as Si-precursor. Indeed, in order to prevent the alteration of the characteristics of the devices which are already present on the wafer, an epitaxy process at low temperature is highly desired for applications such as BiCMOS. In this work, the varying parameters are the deposition temperature, the Si-precursor mass flow and the dopant gas flow. As a result, a process for the deposition of heavily doped epilayers was demonstrated at 600 °C with high deposition rate, which is important for maintaining high throughput and low process cost. We showed that using trisilane as a Si-precursor resulted in a much more linear n-type doping behavior than using dichlorosilane. Therefore it allowed an easier process control and a wider dynamic doping range. Our process is an interesting route for the epitaxy of a low-resistance emitter layer for bipolar transistor application

Vapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition

peer reviewedAtomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 1020 cm-3 at the heterointerface in the Si- cap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles

Growth of high quality InP layers in STI trenches on miscut Si (001) substrates

In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 6° miscut toward (1 1 1) using a thin Ge buffer layer. We studied the impact of growth rates and steric hindrance effects on the nano-twin formation at the STI side walls. It was found that a too high growth rate induces more nano-twins in the layer and results in InP crystal distortion. The STI side wall tapering angle and the substrate miscut angle induced streric hindrance between the InP facets and the STI side walls also contribute to defect formation. In the [-1 1 0] orientated trenches, when the STI side wall tapering angle is larger than 10°, crystal distortion was observed while the substrate miscut angle has no significant impact on the InP defect formation. In the [-1 1 0] trenches, both the increased STI tapering angle and the substrate miscut angle induce high density of defects. With a small STI tapering angle and a thin Ge layer, we obtained extended defect free InP in the top region of the [1 1 0] trenches with aspect ratio larger than 2