Estudo de Parâmetros Analógicos de Transistores SOI MOSFET de Canal Gradual Submicrométricos

O desempenho de transistores SOI de canal gradual (GC) em aplicações analógicas está profundamente relacionado ao desenvolvimento da tecnologia na área da microeletrônica. Superar este desafio requer aperfeiçoar o conhecimento dos parâmetros que caracterizam o dispositivo e confirmar se seu desempenho permanece superior aos transistores uniformemente dopados. O presente estudo traz uma comparação entre transistores SOI submicrométricos convencionais (uniformemente dopados) e GC SOI nMOSFETs com diferentes comprimentos de canal e razão LLD/L. A tensão de limiar, inclinação de sublimiar, máxima transcondutância, condutância de saída, ganho intrínseco de tensão e freqüência de ganho unitário foram usados para esta análise

Broadband parametric amplification for multiplexed SiMOS quantum dot signals

Spins in semiconductor quantum dots hold great promise as building blocks of quantum processors. Trapping them in SiMOS transistor-like devices eases future industrial scale fabrication. Among the potentially scalable readout solutions, gate-based dispersive radiofrequency reflectometry only requires the already existing transistor gates to readout a quantum dot state, relieving the need for additional elements. In this effort towards scalability, traveling-wave superconducting parametric amplifiers significantly enhance the readout signal-to-noise ratio (SNR) by reducing the noise below typical cryogenic low-noise amplifiers, while offering a broad amplification band, essential to multiplex the readout of multiple resonators. In this work, we demonstrate a 3GHz gate-based reflectometry readout of electron charge states trapped in quantum dots formed in SiMOS multi-gate devices, with SNR enhanced thanks to a Josephson traveling-wave parametric amplifier (JTWPA). The broad, tunable 2GHz amplification bandwidth combined with more than 10dB ON/OFF SNR improvement of the JTWPA enables frequency and time division multiplexed readout of interdot transitions, and noise performance near the quantum limit. In addition, owing to a design without superconducting loops and with a metallic ground plane, the JTWPA is flux insensitive and shows stable performances up to a magnetic field of 1.2T at the quantum dot device, compatible with standard SiMOS spin qubit experiments

Electrical characterization and modeling of FDSOI MOSFETs for Cryo-Electronics

International audienceWe present an overview of DC electrical characterization of FDSOI transistors down to very low temperature for cryogenic applications. We also highlight specific phenomena appearing at low temperature, and discuss the corresponding physical and analytical models

Estudo de Parâmetros Analógicos de Transistores SOI MOSFET de Canal Gradual Submicrométricos

O desempenho de transistores SOI de canal gradual (GC) em aplicações analógicas está profundamente relacionado ao desenvolvimento da tecnologia na área da microeletrônica. Superar este desafio requer aperfeiçoar o conhecimento dos parâmetros que caracterizam o dispositivo e confirmar se seu desempenho permanece superior aos transistores uniformemente dopados. O presente estudo traz uma comparação entre transistores SOI submicrométricos convencionais (uniformemente dopados) e GC SOI nMOSFETs com diferentes comprimentos de canal e razão LLD/L. A tensão de limiar, inclinação de sublimiar, máxima transcondutância, condutância de saída, ganho intrínseco de tensão e freqüência de ganho unitário foram usados para esta análise

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs

In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150 K) is presented. This analysis has been carried out through experimental measurements of Common-source, Cascode and Wilson current mirrors architectures. The advantages of the use of graded-channel transistors for implementation of current mirrors in comparison to standard ones is discussed, focusing on the increase of output swing and output resistance. In all architectures some performance degradation has been observed with the temperature reduction, although current mirrors with GC transistors still present better performance than those implemented with standard SOI transistors. Two-dimensional numerical simulations were performed in order to further investigate the behavior of graded-channel current mirrors, looking at the bias condition of each transistor in the current mirror architectures. The obtained results indicate that good performance, compared to that of GC current mirrors, may be obtained by combining both standard and graded-channel transistors, rather than using the same channel engineering for all devices in the circuit

Cryogenic electronics for quantum computing ICs: what can bring FDSOI

International audienceWe present an overview of the performances of FDSOI CMOS transistors down to deep cryogenic temperature, highlighting in particular the benefits brought by the back bias. FDSOI transistors are operational from room temperature down to temperature as lowas 100mK. The main DC electrical characteristics, as well as variability properties and reliability are measured and analyzed.We also point out specific behaviors appearing at cryogenic temperature, and discuss their physical origin and modeling

Cryogenic electronics for quantum computing ICs: what can bring FDSOI

International audienceWe present an overview of the performances of FDSOI CMOS transistors down to deep cryogenic temperature, highlighting in particular the benefits brought by the back bias. FDSOI transistors are operational from room temperature down to temperature as lowas 100mK. The main DC electrical characteristics, as well as variability properties and reliability are measured and analyzed.We also point out specific behaviors appearing at cryogenic temperature, and discuss their physical origin and modeling

Methodology to Separate Channel Conductions of Two Level Vertically Stacked SOI Nanowire MOSFETs

International audienceThis work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (I$_{DS}$) varying the back gate bias (V$_B$), aiming the extraction of carriers' mobility of each level separately. The methodology consists of three main steps and accounts for V$_B$ influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying V$_B$ through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on V$_B$ for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of V$_B$ and up to 150°C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels

New method for individual electrical characterization of stacked SOI nanowire MOSFETs

International audienceA new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom -NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C