Shopping online using the mobile channel: drivers of buying behaviour for Chinese consumers

The emergence of online channels is opening up to new research topics in the retailing literature. Particularly in China, the multifunctional mobile retailing apps, allowing to buy online and socialize the shopping activity with relatives, friends and followers, are supporting the spread of online shopping. A structural equation model combining both traditional antecedents of online shopping - such as ease of use, time convenience, perceived risk - with emerging drivers like perceived price differentiation and shopping socialization is tested to measure the intention to buy using a smartphone by Chinese people. Empirical findings offer new insights for both scholars and practitioners

Syphilis with HIV in Florence, 2003-2009: a 7-year epidemiological study.

SUMMARYThe aims of this study were to describe the trend of acquired syphilis in the city of Florence and its province over a 7-year period, to investigate sexual behaviours in the syphilis-infected population and to analyse syphilis/HIV co-infection. A total of 259 patients were classified according to age, sex and HIV infection. We estimated that from 2004 to 2008 cases increased by 248%. Most patients with concurrent HIV infection were male (31–45 years), but 40- to 60-year-old men who had sex with men predominated in both male and HIV-positive patients. Oral sex was identified as the most significant route of transmission, although most patients did not consider it so. Late-presenters with HIV accounted for 33% of HIV-positive patients: they were unaware of their HIV status and showed syphilis lesions only. In these cases, syphilis heralded the presence of HIV infection and allowed earlier diagnosis

Capacità dinamiche e vantaggio competitivo: un’analisi empirica nel retail

Obiettivi. L’articolo studia il tema delle capacità dinamiche nel retail, verificando l’impatto delle sue componenti sulle performance competitive di un campione di piccoli imprenditori commerciali al dettaglio. Metodologia. La ricerca è stata svolta somministrando un questionario strutturato ad un campione di imprenditori commerciali al dettaglio. I dati raccolti sono stati elaborati applicando una regressione lineare multipla. Risultati. Le evidenze empiriche mostrano come la creazione di conoscenza e di integrazione della stessa impattano in modo significativo e positivo sulle performance competitive, mentre capacità dinamiche legate a processi strutturati di apprendimento e riconfigurazione delle risorse agiscono in senso opposto. Limiti della ricerca. L’articolo esplora come le capacità dinamiche impattano sulle performance di piccoli imprenditori industriali al dettaglio; l’originalità dell’analisi e i pochi studi empirici di riferimento circoscrivono la lettura degli effetti evidenziati, che richiedono ulteriori approfondimenti. Implicazioni pratiche. I piccoli imprenditori commerciali al dettaglio in sede fissa dovrebbero puntare sulla capacità di innovare la propria offerta, rivedendola sia in termini di assortimento offerto che di servizio erogato, migliorando la capacità di alimentare un network con i propri stakeholder, fornitori e clienti in primis. Originalità del lavoro. Ad oggi la letteratura di retail ha scarsamente investigato il tema delle capacità dinamiche, rari sono gli studi empirici sul tema e limitati ad indagini di tipo qualitativo con finalità sostanzialmente esplorative. Il paper intende contribuire a colmare tali gap con una ricerca originale, sulla base di una raccolta dati ad hoc

Design of Shake Table Tests of Multi-Leaf Masonry Walls Before and After Retrofitting

A significant proportion of the built heritage in historic centres is constituted by rubble stone masonry structures. Collapses by leaf separation and disaggregation observed after earthquakes highlight their dramatic vulnerability, especially under out-of-plane loads. Nevertheless, their dynamic response still needs to be fully investigated and their capacity may be overestimated by assessment approaches based on rigid-body mechanics. Effective retrofitting solutions are also needed to protect human lives and safeguard the built heritage, while ensuring the conservation of its architectural value. This paper describes the design of a shake table investigation on stone masonry walls, whose materials and arrangement reproduce those surveyed in the villages of central Italy struck by the 2016-2017 earthquake sequence. The test setup was conceived to induce out-of-plane vertical bending under earthquake base motion and investigate the dynamic response of multi-leaf rubble stone masonry and the gain in seismic capacity that can be achieved with mortar-based composite reinforcements, designed to prevent the leaf separation and disaggregation of the wall without compromising its fair face

A Pixel Read-Out Front-End in 28 nm CMOS with Time and Space Resolution

Future high luminosity colliders will require front-end electronics with unprecedented performance, both in space and time resolution (tens of micrometers and tens of picoseconds) and in radiation hardness (tens of megagray). Moreover, the high number of events will generate an enormous quantity of data (some terabits per second), and the limited bandwidth requires to perform data selection as close as possible to the front-end stage, to reduce the amount of data transmitted and stored for off-line analysis.The TimeSpOT (TIME and SPace real-time Operating Tracker) project, funded by INFN, is developing a complete demonstrator of a tracking device including all the features needed for future high luminosity experiments.In this presentation, we describe the first prototype of the readout electronics in 28 nm CMOS technology. The modules of the front-end circuitry have been designed and integrated in a test chip, which will allow us to characterize each block separately, and to connect them in a processing chain to evaluate the overall performance

Generalized hole-particle transformations and spin reflection positivity in multi-orbital systems

We propose a scheme combining spin reflection positivity and generalized hole-particle and orbital transformations to characterize the symmetry properties of the ground state for some correlated electron models on bipartite lattices. In particular, we rigorously determine at half-filling and for different regions of the parameter space the spin, orbital and $\eta$ pairing pseudospin of the ground state of generalized two-orbital Hubbard models which include the Hund's rule coupling.Comment: 6 pages, 2 figure

Investigation of Rubble-Masonry Wall Construction Practice in Latium, Central Italy

The 2016-2017 Central Italy seismic sequence severely affected existing unreinforced-masonry constructions in four regions. Those in Latium region proved the most prone to fragmentation because of an unfortunate combination of undressed natural stone units and very low lime content in mortar. Within the framework of a research project funded by the regional government, shake table tests are planned to investigate masonry disintegration as well as possible intervention techniques, as described in a companion paper. All specimens will have natural stone units retrieved from the debris in Collespada, a settlement of the municipality of Accumoli, one of the most affected by the seismic sequence. To push further the representativeness of the specimens with respect to field conditions, wall geometry, masonry fabric and mortar recipe are carefully designed. The wall thickness will be approximately equal to 0.5 m, close to average thickness surveyed in the area. Following the survey of several vertical sections of actual masonry walls, the specimens will present unconnected external leaves with a limited nucleus. Based on tests on mortar sampled from collapsed buildings, mortars will be prepared by a part of natural lime every nine parts of sand. Shear tests on sampled mortar delivered apparent cohesion and friction coefficient that are used as preliminary values of a finite-discrete element model, which can account for masonry fragmentation in dynamic non-linear analyses. The numerical model was tested under the envisioned sequence of records, belonging to the Amatrice station and related to the East component, approximately fault normal, of the two main seismic events, 24 August and 30 October, 2016

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started