All-digital self-adaptive PVTA variation aware clock generation system for DFS

An all-digital self-adaptive clock generation system capable of adapt the clock frequency to compensate the effects of PVTA variations on the IC propagation delay and satisfy an externally set propagation length condition is presented. The design uses time-to-digital converters (TDCs) to measure the propagation length and a variable length ring oscillator (VLRO) to synthesize the clock signal. The VLRO naturally adapts its frequency to the PVTA variations suffered by its logic gates while the TDCs are used to track these variations across the chip and modify the VLRO length in order to adapt the clock frequency to them. The system measurements, for a 45nm FPGA, show that it adapts the VLRO length, and therefore the clock frequency, to satisfy the propagation length condition. Measurements also prove the system capabilities to act as a dynamic frequency scaling clock source since the propagation length condition value act as a frequency selection input and a strong linear relation between the input value and the resultant clock period is present.Peer ReviewedPostprint (author’s final draft

Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact

This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 3D TCAD simulations have been performed to obtain a detailed map of the sensitivity areas in a full cell 6-T SRAM 22 nm bulk-FinFET process. The influence of the well depth on the charge collected by the drain devices of the SRAM cell has been studied, and it has been concluded that the collected charge can be reduced down to 300% simply by modifying the depth of the well, without affecting the performance of the cell. Different PTS layer depths have been analyzed in order to calculate which value minimizes the impact of the charge generated by an ion during its track along the FinFET body. The simulations carried out allow to conclude that the incorporation of a PTS layer not only reduces the leakage current, but also reduces the amount of charge, delivered by the ion, that reaches the drain region. Simulation results also show that the fraction of the charge generated by the ion impact, which is collected by the drain, mainly depends on the depth of the wells, whereas the PTS layer hardly modifies the collected charge.Peer ReviewedPostprint (published version

Review on suitable eDRAM configurations for next nano-metric electronics era

We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node.Peer ReviewedPostprint (author's final draft

Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecture

Postprint (published version

Turtle logic: Novel IC digital probabilistic design methodology

Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and consequently signal to noise margins are reduced, exposing computations to higher soft-error rates. In other words, the future circuits will be in a scenario where all devices may fail due to soft-error produced by trend of low SNR. In order to design reliable circuits with unreliable components, novel design techniques have been introduced. The problem of designing reliable systems with unreliable components traces back to Von Neumann, who proposed the N-tuple Modular Redundancy (NMR) technique. Additional proposals have appeared in the literature addressing the problem from the point of view of noise tolerance. For instance, the approach based on Markov Random Field theory (MRF). Take in account the Hamming distance for build basic logic gates focus to high noise and low voltage scenarios. Therefore, our proposal is based on the assumption that the devices in new and future technologies will be not perfect, noisy and hence they might fail.Peer ReviewedPostprint (published version

Eines d’autor: avaluació de noves eines orientades al desenvolupament de competències genèriques per la millora del procés d’aprenentatge autònom dels estudiants

Els cursos on-line massius (Massive Open On-line Courses) estan emergent i suposarà un gran repte en l’educació universitària en els propers anys. Universitats com Standford i MIT han començat aquest any cursos en obert amb una matriculació de centenars de milers d’estudiants en les seves assignatures pilots. Aquests cursos es basen en deixar material docent en servidors, on els estudiants poden seguir en qualsevol moment, i des de qualsevol lloc el curs. Per generar aquest cursos, es necessari tenir bones eines que permetin generar bon material, i que el docent no necessiti concentrar-se en el programari, i si en els mètodes que desitgi aplicar. Dintre d’aquest objectiu, ja des de fa uns anys han aparegut unes eines anomenades “rapid eLearning Tools” que prometen generar materials didàctics de qualitat amb gran facilitat. Entenem per “eines ràpides”, aquelles que, amb uns coneixements a nivell d’usuari d’informàtica, les eines permeten obtenir productes multimèdia de bona qualitat, sense la necessitat de invertir un temps excessiu en la seva generació. Existeixen moltes eines ràpides d’autor a l’actualitat, amb una gran varietat de prestacions. Un dels objectius necessaris és conèixer les ofertes actuals en el mercat dels programaris i tenir una avaluació seguint uns criteris objectius. Aquests s’han definit amb criteris d’us del docent i impacte en el material obtingut.Peer Reviewe

Introducing autonomous vehicles into an unergraduate engineering course

Autonomous vehicles (AVs) are of great interest for the automotive industry and are expected to revolutionize mobility and public transportation. The university can contribute to the design and development of autonomous vehicles both in the field of teaching and in research and technology transfer. In this paper, it is described how this topic is introduced in an undergraduate engineering course, “Implementation of Automatic Control Systems (IACS)”. The IACS course is based on project based learning (PBL) and learning by doing methodologies. Several practical examples that correspond to real automatic systems are discussed throughout the course and one of them, a low-cost AV to which a Raspberry pi has been adapted, forms the basis for a final project of the course. The control algorithms are developed on MATLAB/SIMULINK and are sent to the Raspberry through a wireless communication network. The control objective of the system is the automatic guidance of the vehicle through a single lane indoor closed circuit, the detection and identification of different traffic signals and the automatic response to these signals. Students check the behavior of the vehicle and proceed to make improvements. Based on the assessment of the students and the robustness of the autonomous vehicles, it is time to consolidate this type of project within the course. Students that want to get deeper into the matter have the opportunity to do a final degree project related with the AV

Two examples of approximate arithmetic to reduce hardware complexity and power consumption

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.As the end of Moore's Law approaches, electronic system designers must find ways to keep up with the ever increasing computational demands of the modern era. Some computationally intensive applications, such as multimedia processing, computer vision and artificial intelligence, present a unique feature that makes them especially suitable for hardware-level optimizations: their inherent robustness to noise and errors. This allows circuit designers to relax the constraint that arithmetic operations, such as multiplications and additions, must be completely accurate. Instead, approximations can be used in the arithmetic units, enabling system-level reductions in hardware area and power consumption, as well as improvements in performance, while hardly affecting the output of the final application. In this work, we explore two approximate arithmetic techniques. First, we consider approximations at the circuit design level by implementing several approximate multiplier units and evaluating their accuracy when used in executing YOLOv3, a state-of-the-art camera-based object detection deep neural network. Second, we apply the technique of overscaling to induce approximations in adder circuits by aggressively undervoltaging and overclocking them, and we compare the behavior of exact and approximate adders under these conditions. We find that, on one hand, some approximate multipliers are able to execute the YOLO network with almost no effect on the results, and on the other, approximate adder circuits are much more resilient to overscaling techniques than exact adders.This work was partially supported by Spanish MCIN/AEI/10.13039/501100011033, Project PID2019-103869RB-C33.Peer ReviewedPostprint (author's final draft