Hierarchical Discrete-Event Simulation on Hypercube Architecture

This paper presents model of hierarchical discrete-event simulation algorithm running on a hypercube architecture. We assume a static allocation of system components to processors in the hypercube. We also assume a global clock algorithm, with an event-based time increment. Following development of the performance model, we describe an application of the model in the area of digital systems simulation. Hierarchical levels included are gate level (NAND, NOR, and NOT gates) and MSI level (multiplexors, shift registers, etc.). Example values (gathered from simulations running on standard von Neumann architectures) are provided at the model inputs to show the effect of different model parameters and partitioning strategies on the simulation performance

A Unified Approach to Mixed-Mode Simulation

This paper presents a unified approach to mixed-mode simulation. It investigates the algorithms for both logic and circuit simulation, considering their similarities and differences, and a general framework is presented for integrating the two algorithms in uniform manner. The time advance mechanisms and component functional evaluations of the algorithms are show to be similar in nature, and mechanisms for the translation of information represented uniquely in the two algorithms are given. The resulting integrated algorithms is capable of performing mixed-mode simulation, where a circuit is partitioned into discrete and continuous regions, and each region is simulated at the appropriate level. In addition, several of the issues relating to the implementation of mixed-mode simulation on multiprocessors are presented

Collecting Data About Logic Simulation

Design of high performance hardware and software based gate-switch level logic simulators requires knowledge about the logic simulation process itself. Unfortunately, little data is publically available concerning key aspects of this process. An example of this is the lack of published empirical measurements relating to the time distribution of events generated by such simulators. This paper presents a gate-switch level logic simulator lsim which is oriented towards the collection of data about the simulation process. The basic components of lsim are reviewed, and its relevant data gathering facilities are discussed. An example is presented which illustrates the use of lsim in gathering data on event distributions and on communications requirements under alternative logic circuit partitionings

LSIM2 User\u27s Manual

Lsim2 is gate/switch-level digital logic simulator. It enables users to model digital circuits both at the gate and switch level and incorporates features the support investigation of the simulation task itself. Lsim2 is an augmented version of the original lsim* with the addition of several new MSI-type components models. This user\u27s manual describes procedures for specifying a circuit in lsim2, mechanisms for controlling the simulation, and approaches to modeling systems

Parallel Simulated Annealing

Since the paper by Kirkpatrick, Gelatt and Vecchi in 1983, the use of Simulated Annealing (SA) in solving combinatoric optimization problems has increased substantially. The SA algorithm has been applied to difficult problems in the difficult problems in the digital design automation such as cell placement and wire routing. While these studies have yielded good or near optimum solutions, they have required very long computer execution times (hours and days). These long times, coupled with the recent availability of the number of commercial parallel processors, has prompted the search for parallel implementations of the SA algorithm. The goal ahs been to obtain algorithmic speedup through the exploitation of parallelism. This paper presents a method for mapping the SA algorithm onto a dynamically structured tree of processors. Such a tree of processors can be mapped onto both shared memory and message based styles of parallel processors. The parallel SA (PSA) algorithm is discussed and its performance evaluated using simulation techniques. An important property of the PSA algorithm presented is that it maintains the same move decision sequence as the Serial SA (SSA) algorithm this avoiding problems associated with move conflicts, erroneous move acceptance/rejection decisions and oscillations which have been associated with other PSA algorithm proposals. The PSA algorithm presented fully preserves the convergence properties of the SSA algorithm with speedups varying roughly as log2N where N is the number of processors in the parallel processor

Sorting as a Streaming Application Executing on Chip Multiprocessors

Expressing concurrency in applications has always been a difficult and error-prone endeavor, yet effective utilization of multi-core processors requires that the concurrency in applications be understood. One approach to the expression of concurrency is streaming, which has shown real promise as a safe and effective method for many application classes. Here, we express a classic problem, sorting, in the streaming paradigm and explore the implications of various algorithm and architectural design parameters on the performance of the application

Metal Patch Antenna

Disclosed herein is a patch antenna comprises a planar conductive patch attached to a ground plane by a support member, and a probe connector in electrical communication with the conductive patch arranged to conduct electromagnetic energy to or from the conductive patch, wherein the conductive patch is disposed essentially parallel to the ground plane and is separated from the ground plane by a spacing distance; wherein the support member comprises a plurality of sides disposed about a central axis oriented perpendicular to the conductive patch and the ground plane; wherein the conductive patch is solely supported above the ground plane by the support member; and wherein the support member provides electrical communication between the planer conductive patch and the ground plane

Material Characterization and Real-Time Wear Evaluation of Pistons and Cylinder Liners of the Tiger 131 Military Tank

Material characterisation and wear evaluation of the original and replacement pistons and cylinder-liners of Tiger 131 is reported. Original piston and cylinder-liner were operative in the Tigers’ engine during WWII. The replacement piston and cylinder-liner were used as substitutes and were obtained after failure in two hours of operation in the actual engine. Material characterisation revealed that the original piston was aluminium silicon hypereutectic alloy whereas the replacement piston was aluminium copper alloy with very low silicon content. Both original and replacement cylinder-liners consisted of mostly iron which is indicative of cast iron, a common material for this application. The replacement piston average surface roughness was found to be 9.09 μm while for replacement cylinder-liner it was 5.78 μm