477 research outputs found

    Characterization of charge trapping mechanisms in GaN vertical Fin FETs under positive gate bias

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    In this paper, we present a comprehensive analysis of the charge trapping mechanisms that affect the GaN based vertical Fin FETs when the devices are submitted to positive gate bias. Devices with higher channel width show lower threshold voltage: with 2D simulations of the electron density we are able to explain the phenomenon and propose a trade-off to improve the technology. By using double pulse measurements and threshold voltage transients, two trapping/detrapping mechanisms under positive gate bias can be identified according to two voltage ranges. At low positive gate bias, electrons (previously trapped inside the oxide during the fabrication process) are detrapped towards the gate metal (mechanism 1). At higher gate bias, electrons are trapped at the GaN/oxide interface, moving the threshold towards positive values (mechanism 2). The second mechanism is observable at higher time of stress and it is predominant for higher voltages. Moreover, mechanism 2 is found to be recoverable only when the device is exposed to UV-light and electrons trapped in a specific level in the oxide acquire the energy necessary to escape and reach the n-type GaN and/or the UV-generated holes accumulate at the interface may reduce the trapped electron density. We demonstrate our hypothesis by calculating the interface state density in trapping/detrapping conditions by using photo-assisted Capacitance-Voltage measurements

    Failure Physics and Reliability of GaN-Based HEMTs for Microwave and Millimeter-Wave Applications: A Review of Consolidated Data and Recent Results

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    Herein, the results are reviewed concerning reliability of high-electron mobility transistors (HEMTs) based on GaN, which currently represent the technology of choice for high-efficiency microwave and millimeter-wave power amplifiers. Several failure mechanisms of these devices are extensively studied, including converse piezoelectric effects, formation of conductive percolation paths at the edge of gate toward the drain, surface oxidation of GaN, time-dependent breakdown of GaN buffer, and of field-plate dielectric. For GaN HEMTs with scaled gate length, the simultaneous control of short-channel effects, deep-level dispersion, and hot-electron-induced degradation requires a careful optimization of epitaxial material quality and device design

    Renal Involvement in Multisystem Inflammatory Syndrome in Children: Not Only Acute Kidney Injury

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    Kidney involvement has been poorly investigated in SARS-CoV-2 Multisystem Inflammatory Syndrome in Children (MIS-C). To analyze the spectrum of renal involvement in MIS-C, we performed a single-center retrospective observational study including all MIS-C patients diagnosed at our Pediatric Department between April 2020 and May 2022. Demographic, clinical, pediatric intensive care unit (PICU) admission’s need and laboratory data were collected at onset and after 6 months. Among 55 MIS-C patients enrolled in the study, kidney involvement was present in 20 (36.4%): 13 with acute kidney injury (AKI) and 7 with isolated tubular dysfunction (TD). In eight patients, concomitant AKI and TD was present (AKI-TD). AKI patients needed higher levels of intensive care (PICU: 61.5%, p < 0.001; inotropes: 46.2%, p = 0.002; second-line immuno-therapy: 53.8%, p < 0.001) and showed lower levels of HCO3- (p = 0.012), higher inflammatory markers [neutrophils (p = 0.092), PCT (p = 0.04), IL-6 (p = 0.007)] as compared to no-AKI. TD markers showed that isolated TD presented higher levels of HCO3- and lower inflammatory markers than AKI-TD. Our results indicate a combination of both pre-renal and inflammatory damage in the pathogenesis of kidney injury in MIS-C syndrome. We highlight, for the first time, the presence of tubular involvement in MIS-C, providing new insights in the evaluation of kidney involvement and its management in this condition

    Experimental and Numerical Analysis of OFFState Bias Induced Instabilities in Vertical GaNon-Si Trench MOSFETs

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    We analyzed the threshold-voltage dynamic instabilities induced by OFF-state stress in pseudo-vertical GaN-on-Si Trench MOSFETs (TMOS). Extensive measurements revealed that OFF-state stress experiments induce a progressive increase of threshold voltage (VT), that is fully recoverable only after high-temperature cycles, so that it can appear as permanent degradation at room temperature. VT increase is found to be strongly affected by drain bias and negligibly influenced by gate bias (below threshold). Activation energy (EA) extracted from high- temperature VT recovery experiments was determined to be ≈1 eV. We further characterized pseudo-vertical p-n junction diodes fabricated onto the same wafer as the TMOS’s by means of capacitance iso-thermal spectroscopy (C-ITS). This experiment revealed depletion capacitance (CDEP) instabilities with the same EA as that characterizing the VT instability, leading to the conclusion that trap states present in the epitaxy are the cause of both observations. Numerical device simulations guided the physical interpretation of the observed phenomena, i.e., that donor traps at 1 eV from the conduction band and localized in the p-layer can lead to both VT and CDEP instabilities in the TMOS and in the p-n diode, respectively, by dynamically modulating the effective p-type doping density in the former and the effective depletion layer width in the latter

    Dynamic Behavior of Threshold Voltage and ID-VDS Kink in AlGaN/GaN HEMTs Due to Poole-Frenkel Effect

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    The kink effect in field-effect transistors (FETs) consists in a sudden increase in drain current, during a drain voltage sweep and leading to a higher drain current saturation value. We report new experimental data concerning the dynamic behavior of the "kink" in AlGaN/GaN HEMTs and correlate them with deep levels. The results demonstrate the role of the Poole-Frenkel effect in determining the occurrence of the kink and identify the experimental conditions that make it observable

    degradation of gan on gan vertical diodes submitted to high current stress

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    Abstract GaN-on-GaN vertical devices are expected to find wide application in power electronics, thanks to the high current densities, the low on-resistance and the high breakdown voltage. So far, only few papers on the reliability of GaN-on-GaN vertical devices have been published in the literature. This paper investigates the degradation of GaN-on-GaN pn diodes submitted to stress at high current density. The study was carried out by means of electrical characterization and electroluminescence (EL) measurements. We demonstrate that: (i) when submitted to stress at high current density, the devices show significant changes in the electrical characteristics: an increase in on-resistance/turn-on voltage, an increase in the generation/recombination components, the creation of shunt-paths. (ii) the increase in on-resistance is strongly correlated to the decrease in the EL signal emitted by the diodes. (iii) the degradation kinetics have a square-root dependence on time, indicative of a diffusion process. The results are interpreted by considering that stress induces a diffusion of hydrogen from the highly-p-type doped surface towards the pn junction. This results in a decrease in hole concentration, due to the creation of Mg H bonds, and in a lower hole injection. As a consequence, on-resistance increases while EL signal shows a correlated decrease

    Analysis of threshold voltage instabilities in semi-vertical GaN-on-Si FETs

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    We present a first study of threshold voltage instabilities of semi-vertical GaN-on-Si trench-MOSFETs, based on double pulsed, threshold voltage transient, and UV-Assisted C-V analysis. Under positive gate stress, small negative V th shifts (low stress) and a positive V thshifts (high stress) are observed, ascribed to trapping within the insulator and at the metal/insulator interface. Trapping effects are eliminated through exposure to UV light; wavelength-dependent analysis extracts the threshold de-Trapping energy ≈2.95 eV. UV-Assisted CV measurements describe the distribution of states at the GaN/Al2O3 interface. The described methodology provides an understanding and assessment of trapping mechanisms in vertical GaN transistors

    Exploration of Gate Trench Module for Vertical GaN devices

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    The aim of this work is to present the optimization of the gate trench module for use in vertical GaN devices in terms of cleaning process of the etched surface of the gate trench, thickness of gate dielectric and magnesium concentration of the p-GaN layer. The analysis was carried out by comparing the main DC parameters of devices that differ in surface cleaning process of the gate trench, gate dielectric thickness, and body layer doping. . On the basis of experimental results, we report that: (i) a good cleaning process of the etched GaN surface of the gate trench is a key factor to enhance the device performance, (ii) a gate dielectric >35-nm SiO2 results in a narrow distribution for DC characteristics, (iii) lowering the p-doping in the body layer improves the ON-resistance (RON). Gate capacitance measurements are performed to further confirm the results. Hypotheses on dielectric trapping/detrapping mechanisms under positive and negative gate bias are reported.Comment: 5 pages, 10 figures, submitted to Microelectronics Reliability (Special Issue: 31st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2020
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