Parallel hardware architectures for the cryptographic Tate pairing

Identity-based cryptography uses pairing functions, which are sophisticated bilinear maps defined on elliptic curves. Computing pairings efficiently in software is presently a relevant research topic. Since such functions are very complex and slow in software, dedicated hard- ware (HW) implementations are worthy of being stud- ied, but presently only very preliminary research is avail- able. This work affords the problem of designing paral- lel dedicated HW architectures, i.e.,co-processors, for the Tate pairing, in the case of the Duursma-Lee algorithm in characteristic 3. Formal scheduling methodologies are applied to carry out an extensive exploration of the archi- tectural solution space, evaluating the obtained structures by means of different figures of merit such as computation time, circuit area and combinations thereof.Comparisons with the (few) existing proposals are carried out, show- ing that a large space exists for the efficient parallelHW computation of pairings

Efficient software implementation of AES on 32-bit platforms

Rijndael is the winner algorithm of the AES contest; therefore it should become the most used symmetric-key cryptographic algorithm. One important application of this new standard is cryptography on smart cards. In this paper we present an optimisation of the Rijndael algorithm to speed up execution on 32-bits processors with memory constraints, such as those used in smart cards. First a theoretical analysis of the Rijndael algorithm and of the proposed optimisation is discussed, and then simulation results of the optimised algorithm on different processors are presented and compared with other reference implementations, as known from the technical literature

MTOR and STAT3 pathway hyper-activation is associated with elevated interleukin-6 levels in patients with shwachman-diamond syndrome: Further evidence of lymphoid lineage impairment

Shwachman–Diamond syndrome (SDS) is a rare inherited bone marrow failure syndrome, resulting in neutropenia and a risk of myeloid neoplasia. A mutation in a ribosome maturation factor accounts for almost all of the cases. Lymphoid involvement in SDS has not been well characterized. We recently reported that lymphocyte subpopulations are reduced in SDS patients. We have also shown that the mTOR-STAT3 pathway is hyper-activated in SDS myeloid cell populations. Here we show that mTOR-STAT3 signaling is markedly upregulated in the lymphoid compartment of SDS patients. Furthermore, our data reveal elevated IL-6 levels in cellular supernatants obtained from lymphoblasts, bone marrow mononuclear and mesenchymal stromal cells, and plasma samples obtained from a cohort of 10 patients. Of note, everolimus-mediated inhibition of mTOR signaling is associated with basal state of phosphorylated STAT3. Finally, inhibition of mTOR-STAT3 pathway activation leads to normalization of IL-6 expression in SDS cells. Altogether, our data strengthen the hypothesis that SDS affects both lymphoid and myeloid blood compartment and suggest everolimus as a potential therapeutic agent to reduce excessive mTOR-STAT3 activation in SDS

Brain Activation Patterns Characterizing Different Phases of Motor Action: Execution, Choice and Ideation.

Motor behaviour is controlled by a large set of interacting neural structures, subserving the different components involved in hierarchical motor processes. Few studies have investigated the neural substrate of higher-order motor ideation, i.e. the mental operation of conceiving a movement. The aim of this functional magnetic resonance imaging study was to segregate the neural structures involved in motor ideation from those involved in movement choice and execution. An index finger movement paradigm was adopted, including three different conditions: performing a pre-specified movement, choosing and executing a movement and ideating a movement of choice. The tasks involved either the right or left hand, in separate runs. Neuroimaging results were obtained by comparing the different experimental conditions and computing conjunction maps of the right and left hands for each contrast. Pre-specified movement execution was supported by bilateral fronto-parietal motor regions, the cerebellum and putamen. Choosing and executing finger movement involved mainly left fronto-temporal areas and the anterior cingulate. Motor ideation activated almost exclusively left hemisphere regions, including the inferior, middle and superior frontal regions, middle temporal and middle occipital gyri. These findings show that motor ideation is controlled by a cortical network mainly involved in abstract thinking, cognitive and motor control, semantic and visual imagery processes

Fix Your Eyes in the Space You Could Reach: Neurons in the Macaque Medial Parietal Cortex Prefer Gaze Positions in Peripersonal Space

Interacting in the peripersonal space requires coordinated arm and eye movements to visual targets in depth. In primates, the medial posterior parietal cortex (PPC) represents a crucial node in the process of visual-to-motor signal transformations. The medial PPC area V6A is a key region engaged in the control of these processes because it jointly processes visual information, eye position and arm movement related signals. However, to date, there is no evidence in the medial PPC of spatial encoding in three dimensions. Here, using single neuron recordings in behaving macaques, we studied the neural signals related to binocular eye position in a task that required the monkeys to perform saccades and fixate targets at different locations in peripersonal and extrapersonal space. A significant proportion of neurons were modulated by both gaze direction and depth, i.e., by the location of the foveated target in 3D space. The population activity of these neurons displayed a strong preference for peripersonal space in a time interval around the saccade that preceded fixation and during fixation as well. This preference for targets within reaching distance during both target capturing and fixation suggests that binocular eye position signals are implemented functionally in V6A to support its role in reaching and grasping

Evaluation of Fermi Read-out of the ATLAS Tilecal Prototype

Prototypes of the \fermi{} system have been used to read out a prototype of the \atlas{} hadron calorimeter in a beam test at the CERN SPS. The \fermi{} read-out system, using a compressor and a 40 MHz sampling ADC, is compared to a standard charge integrating read-out by measuring the energy resolution of the calorimeter separately with the two systems on the same events. Signal processing techniques have been designed to optimize the treatment of \fermi{} data. The resulting energy resolution is better than the one obtained with the standard read-out

Power aware design of an elliptic curve coprocessor for 8-bit platforms

Public key cryptography is widely considered as the best building block for key exchange; different public key algorithms are standardized and used in many applications. Among them, ECC (Elliptic Curve Cryptography) is considered the best solution in terms of security, computational requirements and storage need for secret and public keys. Energy consumption is among the main constraints to be considered in wireless sensor networks. In the case of sensor networks, the typical approaches of minimizing latency via a complete hardware coprocessor or reducing area overhead via an efficient implementation of finite field operations might not provide the best solution. In this paper a coprocessor for minimizing both additional resources and power consumption is presented for elliptic curve over binary extension fields, The costs and performances of such new coprocessors are compared with known results, showing that space exists for the reduction of energy consumption without degrading the other performance figures

Comparative cost/performance evaluation of digit-serial multipliers for finite fields of type GF(2n)

Multiplication in finite fields (Galois fields) is a basic operation for cryptography applications. Recent proposals for elliptic code cryptography, require efficient computation of multiplication in finite fields of type GF(2n) for large values of n (150, 200 bits). Digit-serial multiplier VLSI architectures are an attractive solution, being a compromise between purely parallel and serial ones. A comparative study of digit-serial multiplier VLSI architectures, for fields of type GF(2n), is carried out. Such architectures are reviewed, some further optimisations are proposed, and are then implemented in VHDL (CMOS cell library, 0.35 μm, by ST Microelectronics). Figures of merit like time latency, silicon area and power consumption are evaluated by simulation with Synopsis tools, varying parameters like the size n of the field elements and the size k of the blocks of bits being processed in parallel by the digit-serial architectures