Cystic echinococcosis in slaughtered domestic ruminants from Tunisia

A total of 10,818 domestic ruminants (3913 cattle, 2722 sheep, 3779 goats, 404 dromedaries) slaughtered in various abattoirs in Tunisia between 2003 and 2010 were examined for the presence of Echinococcus granulosus hydatid cysts. The prevalence of cystic echinococcosis (CE) was 16.42% in sheep, 8.56% in cattle, 5.94% in dromedaries and 2.88% in goats. CE prevalence increased with age according to an asymptotic model and there was evidence of variation in infection pressure depending on the region of Tunisia where the animals were slaughtered. Cattle appeared to have the highest infection pressure of the species examined. The mean intensity of hepatic cysts was higher than that of pulmonary cysts in all species. The highest mean intensity of infection with E. granulosus larvae was observed in cattle (18.14) followed by sheep (9.58), goats (2.31) and dromedaries (2.12). The abundance of infection increased in a linear fashion with age in all animal species. Cyst abundance varied with species of animal and district of Tunisia. Cysts from dromedaries were more fertile (44.44%) than those from sheep (30.25%), goats (30.32%) and cattle (0.95%). The viability of the protoscoleces from fertile cysts from cattle (78.45%) was higher than those from sheep (70.71%) and camels (69.57%). The lowest protoscolex viability was recorded for hydatid cysts from goats (20.21%). This epidemiological study confirms the importance of CE in all domestic ruminant species, particularly in sheep, throughout Tunisia and emphasizes the need to interrupt parasite transmission by preventive integrated approaches in a CE control programm

Modélisation du logiciel embarqué à différents niveaux d'abstraction en vue de la validation et la synthèse des systèmes monopuces

ISBN: 2-84813-089-XExploring and validating architectural choices related both to hardware platform design and embedded software is a key enabler to reach a convenient performance/cost tradeoff. By analysing classic design flows, it turns out that the major source behind such developpment cost is due to the late integration of hardware and software parts of a multiprocessor system-on-chip (MPSoC) system. In this thesis, we address this problem of late integration by proposing a unified model allowing the joint representation, at different abstraction levels, of the hardware/software architecture. This model is aimed at easing the gradual SoC design while allowing the validation and the evaluation of the resulted performance at each abstraction level. the contributions of this thesis are (1) the definition of a unified representation model of hardware/software architectures at different abstraction levels, (2) the specification of an execution semantic of this unified model in the context of a global cosimulation environment based on SystemC and (3) a methodology for the automatic refinement of these abstract interfaces relying on a composition technology based on the service dependecy graph.L'analyse des flots de conception classiques montre que les causes d'un tel coût de développement peuvent être ramenées, en grande partie, à l'intégration tardive des parties logicielles et matérielles d'un système multiprocesseurs mono puces (MPSoC). Les travaux de cette thèse s'intéressent à ce problème d'intégration tardive en proposant un modèle unifié permettant la représentation conjointe à différent nivaux d'abstraction des architectures logicielles/matérielles. Ce modèle doit faciliter la conception graduelle de ces architectures tout en permettant la validation et l'évaluation, à chaque niveau d'abstraction, des performances qui en découlent. Les contributions apportées par cette thèse sont (1) la définition d'un modèle de représentation unifié et à différents niveaux d'abstraction des architectures logicielles/matérielles des systèmes MPSoC basé sur le concept d'interface abstraite logiciel/matériel, (2) la spécification d'une sémantique d'exécution de ce modèle dans le cadre d'un environnement de cosimulation globale basé sur SystemC et (3) la proposition d'une méthodologie de raffinement automatique de ces interfaces abstraites exploitant une technologie de composition à base de graphe de dépendance de services

Fast and Accurate Timed Execution of High Level Embedded Software Using HW/SW Interface Simulation Model

Abstract- In this paper, we propose a methodology to perform early design stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS abstraction level and a HW platform described at an arbitrary abstraction level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an early design stage before the system design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86 % compared with a HW/SW cosimulation with ISS). 1

A NEW APPROACH FOR SPARSE PHASE RETRIEVAL BASED ON SUPPORT LIFTING AND LEAST SQUARE ESTIMATION

To recover a signal x from the magnitude of a possible linear transform of it, problem known as Phase Retrieval (PR), signal sparsity property has been used to guide the uniqueness of the solution. This paper presents herein a new method for sparse phase retrieval (SPR). Based on a lifting operation, we reduce the problem of SPR to solving a linear system with regards to a vectorized version of xx T. We then use the struc-tured sparsity property of this vectorized form to interpret this operation rather as a lifting operation of the signal support. The signal support is identified iteratively using the gradient pursuit principle in conjunction with subsequent refinements aiming to control the stability of the updated solution. A simple least square estimation on the lifted support is then brought out, iteratively and if required, to determine the lifted solution; from which a rank−1 decomposition is achieved to recover the signal of interest. Simulation results confirm the efficiency of the so-called Greedy Support-Lifting Based algorithm (GSuLA) with acceptable complexity. Robustness of the algorithm is also assured for noisy measurements

Programming models and HW-SW Interfaces Abstraction for Multi-Processor SoC

ISSN: 0738-100XFor the design of classic computers the Parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to existing multiprocessor platforms using a low level software layer that implements the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hardware and software refinements. This paper deals with parallel programming models to abstract both hardware and software interfaces in the case of heterogeneous MPSoC design. Different abstraction levels will be needed. For the long term, the use of higher level programming models will open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs