Face or building superiority in peripheral vision reversed by task requirements

Peripheral vision has been the topic of few studies compared with central vision. Nevertheless, given that visual information covers all the visual field and that relevant information can originate from highly eccentric positions, the understanding of peripheral vision abilities for object perception seems essential. The poorer resolution of peripheral vision would first suggest that objects requiring large-scale feature integration such as buildings would be better processed than objects requiring finer analysis such as faces. Nevertheless, task requirements also determine the information (coarse or fine) necessary for a given object to be processed. We therefore investigated how task and eccentricity modulate object processing in peripheral vision. Three experiments were carried out requiring finer or coarser information processing of faces and buildings presented in central and peripheral vision. Our results showed that buildings were better judged as identical or familiar in periphery whilst faces were better categorised. We conclude that this superiority for a given stimulus in peripheral vision results (a) from the available information, which depends on the decrease of resolution with eccentricity, and (b) from the useful information, which depends on both the task and the semantic category

Observation of 1D Behavior in Si Nanowires: Toward High-Performance TFETs

This article provides experimental evidence of one-dimensional behavior of silicon (Si) nanowires (NWs) at low-temperature through both transfer (Id−VG) and capaci- tance−voltage characteristics. For the first time, operation of Si NWs in the quantum capacitance limit (QCL) is experimentally demonstrated and quantitatively analyzed. This is of relevance since working in the QCL may allow, e.g., tunneling field-effect transistors (TFETs) to achieve higher on-state currents (Ion) and larger on-/off-state current ratios (Ion/Ioff), thus addressing one of the most severe limitations of TFETs. Comparison of the experimental data with simulations finds excellent agreement using a simple capacitor model

Asymmetrically strained all-silicon Tunnel FETs featuring 1V operation

This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/I off characteristics. We demonstrate that a lateral strain profile with a maximum of strain higher than 3GPa at the BTB source junction could act as an effective performance Tunnel FET enabling the cancelation of the drain threshold voltage. We study and report in detail the contributions of main technology boosters of all-silicon Tunnel FETs: (i) strained source, (ii) high-k gate dielectric, (iii) multiple-gate, (iv) oxide alignment to i-region and (v) channel length scaling, as an additive device optimization enabling future sub-IV operation. ©2009 IEEE

Small Slope Switches

Power dissipation in switching devices is considered today as the most important roadblock for future nanoelectronic circuits and systems. The complementary metal-oxide-semiconductor (CMOS) power consumption consists of two contributions: the dynamic and the static leakage components. The tunnel metal-oxide-semiconductor field-effect transistor (MOSFET) offers an appealing concept for a substantial lowering of the energy dissipated in a switching device by replacing the thermionic emission of charge carriers over a barrier to enter the MOSFET channel with a tunneling process. If the tunneling process is made sufficiently effective, tunnel FETs can ultimately yield an effective cooling of the injecting source contact through a band-pass filter action that enables steep inverse subthreshold slopes over many orders of magnitude, thus providing low values of the average subthreshold swing. This chapter focuses on the characteristics of metal-ferroelectric-MOS structures recently reported by EPFL group based on a complete set of experiments exploiting the internal metal contact