Reconfigurable FPGA implementation of the AVC quantiser and de-quantiser blocks

As image and video resolution continues to increase, compression plays a vital role in the successful transmission of video and image data over a limited bandwidth channel. Computation complexity, as well as the utilization of resources and power, keep increasing when we move from the H264 codec to the H265 codec. Optimizations in each particular block of the Advanced Video Coding (AVC) standard significantly improve the operating frequency of a hardware implementation. In this paper, we designed parametrized reconfigurable quantiser and de-quantiser blocks of AVC through dynamic circuit specialization, which is different from traditional reconfiguration of FPGA. We implemented the design on a Zynq-SoC board, which resulted in optimizations in resource consumption of 14.1{\%} and 20.6{\%} for the quantiser and de-quantiser blocks respectively, compared to non-reconfigurable versions

On predicting the HEVC intra quad-tree partitioning with tunable energy and rate-distortion

International audienceFuture evolutions of the Internet of Things (IoT) are likely to boost mobile video demand to an unprecedented level. A large number of battery-powered systems will then integrate an High Efficiency Video Coding (Hevc) codec, implementing the latest video encoding standard from MPEG, and these systems will need to be energy efficient. Constraining the energy consumption of Hevc encoders is a challenging task, especially for embedded applications based on software encoders. The most efficient approach to manage the energy consumption of an Hevc encoder consists of optimizing the quad-tree partitioning and balance compression efficiency and energy consumption. The quad-tree partitioning splits the image into encoding units of variable sizes. The optimal size for a unit is content dependent and affects the encoding efficiency. Finding this optimal repartition is complex and the energy required by the so-called rate-distortion optimization (RDO) process dominates the encoder energy consumption. For the purpose of budgeting the energy consumption of a real-time Hevc encoder, we propose in this paper a variance-aware quad-tree prediction that limits the energetic cost of the RDO process. The predictor is moreover adjustable by two parameters, (Δ––,Δ¯¯¯¯), offering a trade-off between energetic gains and compression efficiency. Experimental results show that the proposed energy reduction scheme is able to reduce the energy consumption of a real-time Hevc encoder by 45–62% for a bit rate increase of, respectively, 0.49 and 3.4%. Moreover, the flexibility offered by parameters (Δ––,Δ¯¯¯¯) opens new opportunities for energy-aware encoding management