Policy-Driven Memory Protection for Reconfigurable Hardware

Abstract. While processor based systems often enforce memory pro-tection to prevent the unintended sharing of data between processes, current systems built around reconfigurable hardware typically offer no such protection. Several reconfigurable cores are often integrated onto a single chip where they share external resources such as memory. While this enables small form factor and low cost designs, it opens up the op-portunity for modules to intercept or even interfere with the operation of one another. We investigate the design and synthesis of a memory protection mechanism capable of enforcing policies expressed as a formal language. Our approach includes a specialized compiler that translates a policy of legal sharing to reconfigurable logic blocks which can be di-rectly transferred to an FPGA. The efficiency of our access language design flow is evaluated in terms of area and cycle time across a variety of security scenarios

Development of weather-based predictive models for Fusarium head blight and Deoxynivalenol accumulation for spring malting barley

The associations between Fusarium head blight (FHB), caused by Gibberella zeae, and deoxynivalenol (DON) accumulation in spring malting barley (Hordeum vulgare) and hourly weather conditions predictive of DON accumulation were examined using data from six growing seasons in the U.S. Northern Great Plains. Three commonly grown cultivars were planted throughout the region, and FHB disease and DON concentration were recorded. Nine predictor variables were calculated using hourly temperature and relative humidity during the 10 days preceding full head spike emergence. Simple logistic regression models were developed using these predictor variables based on a binary threshold for DON of 0.5 mg/kg. Four of the nine models had sensitivity greater than 80%, and specificity of these models ranged from 67 to 84% (n = 150). The most useful predictor was the joint effect of average hourly temperature and a weighted duration of uninterrupted hours (h) with relative humidity greater than or equal to 90%. The results of this study confirm that FHB incidence is significantly associated with DON accumulation in the grain and that weather conditions prior to full head emergence could be used to accurately predict the risk of economically significant DON accumulation for spring malting barley

Policy-Driven Memory Protection for Reconfigurable Hardware [presentation]

Proceedings of the 11th European Symposium on Research in Computer Security (ESORICS), Hamburg, Germany, September 2006, Pages 461-478. [Paper] [Conference] [Slides

A stochastic bitwidth estimation technique for compact and low-power custom processors

There is an increasing trend toward compiling from C to custom hardware for designing embedded systems in which the area and power consumption of application-specific functional units, registers, and memory blocks are heavily dependent on the bit-widths of integer operands used in computations. The actual bit-width required to store the values assigned to an integer variable during the execution of a program will not, in general, match the built-in C data types. Thus, precious area is wasted if the built-in data type sizes are used to declare the size of integer operands. In this paper, we introduce stochastic bit-width estimation that follows a simulation-based probabilistic approach to estimate the bit-widths of integer variables using extreme value theory. The estimation technique is also empirically compared to two compile-time integer bit-width analysis techniques. Our experimental results show that the stochastic bit-width estimation technique dramatically reduces integer bit-widths and, therefore, enables more compact and power-efficient custom hardware designs than the compile-time integer bit-width analysis techniques. Up to 37% reduction in custom hardware area and 30% reduction in logic power consumption using stochastic bit-width estimation can be attained over ten integer applications implemented on an FPGA chip