Fast Motion Estimation’s Configuration Using Diamond Pattern and ECU, CFM, and ESD Modes for Reducing HEVC Computational Complexity

The high performance of the high efficiency video coding (HEVC) video standard makes it more suitable for high-definition resolutions. Nevertheless, this encoding performance is coupled with a tremendous encoding complexity compared to the earlier H264 video codec. The HEVC complexity is mainly a return to the motion estimation (ME) module that represents the important part of encoding time which makes several researches turn around the optimization of this module. Some works are interested in hardware solutions exploiting the parallel processing of FPGA, GPU, or other multicore architectures, and other works are focused on software optimizations by inducing fast mode decision algorithms. In this context, this article proposes a fast HEVC encoder configuration to speed up the encoding process. The fast configuration uses different options such as the early skip detection (ESD), the early CU termination (ECU), and the coded block flag (CBF) fast method (CFM) modes. Regarding the algorithm of ME, the diamond search (DS) is used in the encoding process through several video resolutions. A time saving around 46.75% is obtained with an acceptable distortion in terms of video quality and bitrate compared to the reference test model HM.16.2. Our contribution is compared to other works for better evaluation

An efficient and unified 2D-inverse integer cosine transform (IICT) FPGA-hardware implementation for HEVC standard

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An optimized and unified architecture design for H.265/HEVC 1-D inverse core transform

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Fast motion estimation for HEVC video coding

International audience—In this paper, a fast configuration for Motion Estimation (ME) is described in order to reduce the computational time of the new High Efficient Video Coding (HEVC). This configuration uses the Coded Block Flag (CBF) Fast Method (CFM), the Early Coding Unit (CU) termination (ECU) and the Early Skip Detection (ESD) modes. The Diamond Pattern is used as a search algorithm for ME in the encoding process. Compared to the latest original reference software test model (HM) 16.2 of the HEVC, experimental results had showed that the complexity is reduced, in average, by 56.75% with a small bit-rate and PSNR degradation

Hardware implementation of 1-D 8-point adaptive multiple transform in post-HEVC standard

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OpenVVC Decoder Parameterized and Interfaced Synchronous Dataflow (PiSDF) Model: Tile Based Parallelism

International audienceThe emergence of the new video coding standard, Versatile Video Coding (VVC), has resulted in a 40-50% coding gain over its predecessor HEVC for the same visual quality. However, this is accompanied by a sharp increase in computational complexity. The emergence of the VVC standard and the increase in video resolution have exceeded the capacity of single-core architectures. This fact has led researchers to use multicore architectures for the implementation of video standards and to use the parallelism of these architectures for real-time applications. With the strong growth in both areas, video coding and multicore architecture, there is a great need for a design methodology that facilitates the exploration of heterogeneous multicore architectures, which automatically generates optimized code for these architectures in order to reduce time to market. In this context, this paper aims to use the methodology based on data flow modeling associated with the PREESM software. This paper shows how the software has been used to model a complete standard VVC video decoder using Parameterized and Interfaced Synchronous Dataflow (PiSDF) model. The proposed model takes advantage of the parallelism strategies of the OpenVVC decoder and in particular the tile-based parallelism. Experimental results show that the speed of the VVC decoder in PiSDF is slightly higher than the OpenVVC decoder handwritten in C/C++ languages, by up to 11% speedup on a 24-core processor. Thus, the proposed decoder outperforms the state-of-the-art dataflow decoders based on the RVC-CAL model

Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard

International audienceVersatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. Several new contributions have been proposed to enhance the coding efficiency beyond the High Efficiency Video Coding (HEVC) standard. One of these tools is the Adaptive Multiple Transform (AMT) as a new approach of the transform core design. The AMT involves five DCT/DST transform types with larger and more flexible partitioning block sizes. However, the AMT coding efficiency comes with the cost of higher computational complexity, especially at the encoder side. In this paper, a efficient pipelined hardware implementation of the AMT including the five types of sizes 4x4, 8x8, 16x16 and 32x32 is proposed. The architecture design takes advantage of the internal software/hardware resources of the target FPGA device such as Library of Parametrized Modules (LPM) core IPs and blue Digital Signal Processing (DSP) blocks. The proposed 1D 32-point AMT design allows to process 4K video at 44 frames per second. A unified 2D implementation of the 4, 8, 16 and 32-point AMT design is also presented.The implementation takes into account all the asymmetric 2D block size combinations from 4 to 32. The 2D architecture design is able to sustain 2K video coding at 50 frames per second with an operational frequency up to 147 Mhz

Multiple Transform Selection Concept Modeling and Implementation Using Dynamic and Parameterized Dataflow Graphs

International audienceThe new video coding standard, Versatile Video Coding (VVC), released by the end of 2020 has increased the coding complexity both at encoder and decoder sides. This complexity increase is due to several coding tools proposed to enhance the coding efficiency. One of these tools is the Multiple Transform Selection (MTS) concept, a new approach for the transform unit. This paper aims at providing a new optimization of the MTS based on dataflow modeling. The proposed approach takes benefit of the different parallelism levels of the MTS in order to create an optimized multicore implementation. Also, this paper study the impact of the dataflow model granularity and the dynamic reconfiguration on the implementation efficiency on x86 multicore architectures. The PREESM tool is used in this study to develop the proposed dataflow models and for the granularity analysis. The dynamic reconfiguration study is here performed using the SPIDER runtime optimized for the multicore execution of applications modeled using Parameterized and Interfaced Synchronous Dataflow (PiSDF) dataflow graphs. Two architectures were used in this work: an x86 architecture with 4 cores and an x86 architecture with 24 cores. The results show that the SPIDER overhead time is almost negligible (0.05%) compared to the execution time of the application. Furthermore, a speed-up of 3.9 and up to 22 for all block sizes was achieved using a 4-core and 24-core machine, respectively

Structural characterization and functional properties of antihypertensive Cymodocea nodosa sulfated polysaccharide

A sulfated polysaccharide was successfully isolated from Cymodocea nodosa (CNSP). This is the first report that indicates the chemical composition, structural characterization, functional and antihypertensive properties of this polysaccharide. The CNSP consisted mainly of sulfate (23.17%), total sugars (54.90%), galactose (44.89%), mannose (17.30%), arabinose (12.05%), xylose (9.18%), maltose (1.07%) and uronic acid (11.03%) with low water activity (0.49). CNSP had an XRD pattern that was typical for a semi-crystalline polymer with homogeneous structure. It also displayed an important anti-hypertensive activity (IC50 = 0.43 mg ml) with a dose-dependent manner using a synthetic substrate, N-hippuryl-His-Leu hydrate salt (HHL). Overall, the results indicate that CNSP have attractive chemical, functional and biological properties, with a preliminary structural may have a backbone of branched 6-O-sulfated (1 → 4) galactosidic linkages, which can be considered in the future as alternative additive in various foods, cosmetic and pharmaceutical preparations