Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard

Abstract

International audienceVersatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. Several new contributions have been proposed to enhance the coding efficiency beyond the High Efficiency Video Coding (HEVC) standard. One of these tools is the Adaptive Multiple Transform (AMT) as a new approach of the transform core design. The AMT involves five DCT/DST transform types with larger and more flexible partitioning block sizes. However, the AMT coding efficiency comes with the cost of higher computational complexity, especially at the encoder side. In this paper, a efficient pipelined hardware implementation of the AMT including the five types of sizes 4x4, 8x8, 16x16 and 32x32 is proposed. The architecture design takes advantage of the internal software/hardware resources of the target FPGA device such as Library of Parametrized Modules (LPM) core IPs and blue Digital Signal Processing (DSP) blocks. The proposed 1D 32-point AMT design allows to process 4K video at 44 frames per second. A unified 2D implementation of the 4, 8, 16 and 32-point AMT design is also presented.The implementation takes into account all the asymmetric 2D block size combinations from 4 to 32. The 2D architecture design is able to sustain 2K video coding at 50 frames per second with an operational frequency up to 147 Mhz