Advances, Challenges and Opportunities in 3D CMOS Sequential Integration

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications

Inter-tier electrostatic coupling effects in 3D sequential integration devices and circuits

International audienceThis work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier coupling impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and ΔIon might reach high values, it is demonstrated that regarding digital applications, the coupling-induced fluctuations are well below the mismatch effects. TCAD and SPICE simulations were used to fully understand the phenomenon, to predict the effects at SRAM bitcell level and to propose guidelines to contain the inter-tier electrostatic coupling: the coupling effect can be limited either by increasing the Inter-Layer Dielectric (ILD) thickness or through a top/bottom transistor misalignment

Statistical Characterization and Modelling of Gate-Induced Drain Leakage Variability in Advanced FDSOI Devices

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Guidelines on 3D VLSI design regarding the intermediate BEOL process influence

International audienceThis paper aims at identifying the critical parameters for intermediate back end of line (BEOL) in 3DVLSI in order to benefit from higher circuit gain in performance. Thanks to circuit simulations in a 3D environment PDK, the capacitance is identified as the most critical parameter for IC performance of circuits using two intermetal levels. The critical wirelength upon which a gain in performance is obtained by the 3D stacking is evaluated as a function of BEOL flavor

An atomistic investigation of the impact of in-plane uniaxial stress during solid phase epitaxial regrowth

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Self-heating assessment and cold current extraction in FDSOI MOSFETs

session: Modeling and CharacterizationInternational audienceWe present an experimental study of thermal effects in thin film FDSOI MOSFETs, with a focus on the impact of self-heating effect (SHE) on drain current. We have performed thermal resistance extraction using the gate thermometry method, and calculated the resulting cold drain current (Id0), i.e. without SHE. We demonstrate that SHE is more pronounced in shorter and narrower devices without essential differences between nMOS and pMOS transistors. Our experiments show that although the temperature increases significantly in the channel due to SHE, its effect on the ION performances could be limited at operating voltage

RF Performance of Devices Processed in Low-Temperature Sequential Integration

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NiCo 10 at%: A promising silicide alternative to NiPt 15 at% for thermal stability improvement in 3DVLSI integration

3D VLSI with a CoolCube TM process allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. The thermal budget allowed to process the top transistor is currently limited by NiPt silicide stability of the bottom transistor. To extend the upper transistors thermal process window, Pre-Amorphization Implant (PAI) and Si-Capping were used to improve the stability of NiPt 15% on SiC:P and SiGe 30% :B accesses. While PAI enhances the silicide stability on SiC:P substrate from 600°C 2h to 700°C 2h, neither PAI nor Si-Capping improve silicide stability on SiGe 30% :B. To provide a solution for P accesses stability, NiCo 10% silicidation has been developed. Combined with PAI and Si-Capping, the germano-silicide offers a higher stability (up to 600°C 2h) than its NiPtSi 15% counterpart