Academic Use of Rapid Prototyping in Digitally Controlled Power Factor Correctors

The growing use of power converters connected to the grid motivates their study in power electronics courses and the prototype development in the degree final project (DFP). However, the practical realization of using state-of-the-art components and conversion techniques is complex due to the numerous multidisciplinary aspects that students must consider in its design and development and the workload associated with the DFP. An example of this is that, unlike a conventional power factor correction (PFC) design, the individual dedication of students to complete the design and validation of modern bridgeless PFC stages exceeds the number of credits of the DFP. The reason for this is that it includes system modeling, becoming familiar with the devices used, discrete selection, circuit design, control development, and programming, to build the converter and verify the operation of the complete system. To reinforce the individual skills needed for the DFP and reduce this time, a novel strategy is proposed. It allows the student to focus their efforts on integrating the individual skills achieved in the degree at the appropriate competence level during the modeling and construction of the power converter while carrying out part of the tasks out of the lab, if necessary, as was the case during the pandemic restrictions. For this, the rapid prototyping technique is introduced to speed up the overall design and speed up the tuning of digital controllers. This manuscript presents a teaching experience in which students build digitally controlled power converters using Texas Instruments microcontroller boards and PLECS®. The example of a bridgeless totem-pole power factor corrector is shown. Although it began to develop and was motivated due to the restrictions during the COVID-19 pandemic, the experience has been verified and is maintained over time, successfully consolidating

Pre-Calculated Duty Cycle Control Implemented in FPGA for Power Factor Correction

A power factor correction (PFC) technique based on pre-calculated duty cycle values is presented in this paper. In this method the duty ratios for half a line period are calculated in advance and stored in a memory. By synchronizing the memory with the line, near unity power factors can be achieved in a specific operating point. The main advantage of this technique is that neither current measurement nor current loop are needed. To obtain stable output voltages a voltage loop is included. A boost converter prototype controlled by an FPGA evaluation board has been implemented in order to verify the functionality of the proposed method. Both the simulation and experimental results show that near unity power factor can be achieved with this PFC strategy

Corrección del factor de potencia, sin medida de corriente, mediante implementación en FPGA de one-cycle control

En este artículo se presenta una técnica de control digital de correctores de factor de potencia (CFP) trabajando en modo de conducción continua en la que no es necesario el uso de sensor de corriente ni de convertidor analógico-digital de alta velocidad. La corriente de entrada al CFP se estima a partir de la descripción del modelo en VHDL de un convertidor elevador y de las muestras digitales de las tensiones de entrada y salida del convertidor. El objetivo final es desarrollar un controlador universal para CFP, con posibilidad de trabajar varios convertidores idénticos en paralelo y así aumentar la potencia. En este trabajo se abordan las diferentes soluciones ante los problemas que aparecen en el desarrollo del prototipo de laboratorio y se presentan resultados en diferentes condiciones, comparando el contenido armónico de la corriente con los límites establecidos por la normativa vigente más restrictiv

Current sensorless power factor correction based on digital current rebuilding

A new digital control technique for power factor correction is presented. The main novelty of the method is that there is no current sensor. Instead, the input current is digitally rebuilt, using the estimated input current for the current loop. Apart from that, the ADCs used for the acquisition of the input and output voltages have been designed ad-hoc. Taking advantage of the slow dynamic behavior of these voltages, almost completely digital ADCs have been designed, leaving only a comparator and an RC filter in the analog part. The final objective is obtaining a low cost digital controller which can be easily integrated in an ASIC along with the controller of paralleled and subsequent power section

Acoustic Noise-Based Detection of Ferroresonance Events in Isolated Neutral Power Systems with Inductive Voltage Transformers

Power-quality events and operation transients in power systems (PS) with isolated neutral can saturate inductive voltage transformers (IVT), which, when interacting with the overhead and underground cable capacitances, can cause ferroresonance events in the local PS. This abnormal operating mode can partially or totally damage the transformers and switchgears within the affected PS. Distribution system operators (DSO) can minimize these effects by detecting ferroresonance events accurately and fast enough and changing the mode of operation accordingly. Direct detection methods, i.e., based on voltage measurements, are reliable, but the massive deployment of this solution is relatively expensive; i.e., power quality analyzers cost thousands of USD. Alternatively, indirect detection methods are also available, e.g., IVT vibration measurements with accelerometers costing hundreds of USD, but their reliability depends on the installation method used. This manuscript proposes using the acoustic noise caused by magnetostriction forces within the IVT core during ferroresonance events to detect their occurrence. Compared to other indirect methods, electret condenser microphones with preamplifying stage cost less than USD 10 and are less sensitive to the installation procedure. The proposed method is validated experimentally, and its performance compared to IVT vibration measurements one by using the same detection methodology.This work was partially financed by the EU Regional Development Fund (FEDER) and the Spanish Government under RETOS-COLABORACION RTC-2017-6782-3, the Spanish Ministry of Science and Innovation under project PID2021-128941OB-I00, and by the European Union’s Horizon 2020 research and innovation program under grant agreement No. 864579 (FLEXIGRID)

Improved Noise Immunity for Two-Sample PLL Applicable to Single-Phase PFCs

Synchronization in a single-phase Power Factor Correction (PFC) is deteriorated, among others, by the combination of the noise introduced by the grid voltage sensing, conducted EMI, the ADC resolution and the sampling frequency used. Low signal-to-noise ratios (SNR) reduce the performance of the Two-Sample (2S) Phase Locked Loop (PLL). This effect can be compensated by including a smoothing filter action without increasing the overall complexity significantly. The resulting 2S with smoothing (2SS) is evaluated and validated by simulation and experimentally over a Totem Pole PFC

Envelope-based Modeling for Single-Phase Grid-Following and Forming Converters

The study of the interaction with the grid, including synchronization, controller design and stability assessment for 1f grid-following (GFL) and grid-forming (GFM) power converters requires an efficient modeling tool to design universal grid-connected converters considering the different grid scenarios. From the initial time-periodic system, approximated linear time-invariant (LTI) models are obtained through dynamic phasors, linearization of variables represented in a virtual synchronous rotating reference frame (RRF) or linearization in the frequency domain, i.e. harmonic linearization. The accuracy and complexity of the obtained model depend on the method used. This work proposes to use the well-known envelope modeling approach used for resonant converters but requiring the time periodic input to generate its related phase synchronization for the model. The result is a simple and accurate LTI model of 1fGFL/GFM power converter for such stability studies. The proposed 1f modeling approach is valid for any application with phase locked loop (PLL) synchronization. Simulation results validating de proposal are provided

Frequency Estimation in DSOGI cells by means of the Teager Energy Operator

Second Order Generalized Integrator (SOGI) cells are used for notch filtering due to their simplicity and harmonic rejection capability. SOGI and Dual SOGI (DSOGI) filter cells, combined with Frequency Locked Loops (FLL) to adjust the notch frequency, are commonly used in both single-and three-phase grid following (GFL) power converters for synchronization, i.e. SOGI-FLL and DSOGI-FLL, respectively. The FLL relies on a gradient descent method to minimize a cost function built up around one inner SOGI cell variable, the in-quadrature voltage estimation, and one outer variable, the error signal due to the SOGI filter cell. As a result, the FLL generates relatively large DC offsets and harmonic distortion passing through the outer SOGI cell variable, which deteriorates the frequency estimation and then, the SOGI-FLL performance. To attenuate these issues, the method proposed only uses inner SOGI cell variables. It minimizes the deviation between the estimated grid frequency and the frequency of the signal across the SOGI cell, which is detected through the Teager Energy Operator (TEO). The proposal is validated in simulation and experimentally

Self-balanced Two-output Battery Charger

The design and modeling of a self-balanced two-output battery charger capable to charge two high-power LiFePO4 battery packs is presented. The proposal is based on a four-phase resonant converter, which is designed as a voltage-controlled current-source, working at constant switching frequency. The output stage consists of a transformer with a single primary and two secondaries implementing two current-doubler rectifiers. The structure of the output stage naturally imposes the self-balance-of-charge of both battery packs provided that the coupling between the primary and each of the secondaries has a negligible mismatch. The electrical model of the battery is used to study the batteries charge equalization during the charging process considering the non-idealities of the output transformer. The theoretical analysis and design procedure of the proposed battery charger is fully explained. The output current capability and efficiency are validated experimentally considering a 50 Ah 48 V commercial battery pack