Are all students 'hard to reach' in a digital higher education (H.E.) context?

Students entering Higher Education (HE) have high levels of digital capability built on the need to be socially-connected; they should be 'easy to reach’ if thinking about connectivity underpinning the digital age. Yet findings based on commissioned work exploring digital capability and teaching excellence (Austen et al, 2016) indicate that student appraisals of this relationship relate to the logistical benefits of technology rather than to the development of capabilities for professional practice, i.e. the multi-faceted set of academic and information-retrieval skills. Our study highlights a pedagogical challenge in needing to re-frame digital capability for all learners new to HE as this 'hard to reach' phenomenon is maintained by a student focus on technological hygiene factors rather than supported risk-taking

Digital capability and teaching excellence: an integrative review exploring what infrastructure and strategies are necessary to support effective use of technology enabled learning (TEL)

This report is set within the evolving landscape of UK Higher Education (HE) in which an increasingly marketised HE economy has led to a changing relationship with students and wider stakeholders. The proposed introduction of the Teaching Excellence Framework (TEF) (Department for Business, Innovation and Skills, 2016) aims to recognise and reward excellent learning and teaching. This integrative review provides timely evidence concerning the relationship of digital capability and teaching excellence. Keywords: teaching excellence, digital capabilit

Mapping the Free Energy of Lithium Solvation in the Protic Ionic Liquid Ethylammonuim Nitrate: A Metadynamics Study

Understanding lithium solvation and transport in ionic liquids is important due to their possible application in electrochemical devices. Using first-principles simulations aided by a metadynamics approach we study the free-energy landscape for lithium ions at infinite dilution in ethylammonium nitrate, a protic ionic liquid. We analyze the local structure of the liquid around the lithium cation and obtain a quantitative picture in agreement with experimental findings. Our simulations show that the lowest two free energy minima correspond to conformations with the lithium ion being solvated either by three or four nitrate ions with a transition barrier between them of 0.2 \eV. Other less probable conformations having different solvation pattern are also investigated

Architectures for transactional memory

Engineers have successfully worked for decades to improve single thread CPU performance, but we have now reached a peak in what a single thread can do. Average programmers are now facing the eventuality that their code must be parallel to take advantage of the performance potential of multi-core chips. Unfortunately, writing parallel programs is hard because synchronizing accesses to shared state is complex and error-prone—many techniques have been tried, but achieving performance and correctness simultaneously still requires expert programmers, and the method of choice is decades old (locks). Transactional Memory (TM) is a relatively new programming paradigm promising an easier road to correctness and performance using atomic code regions. These regions may then be speculatively executed in parallel, potentially providing performance gains. This dissertation focuses on architecting and evaluating hardware TM systems. We begin by briefly arguing that TM should be implemented in hardware, since proposed software solutions suffer from poor performance. We then study qualitatively and quantitatively the large design space for hardware TM as defined by primary options such as version management and conflict detection, and vary the secondary options such as the structure of the memory hierarchy, the instructions per cycle, and the configuration of the interconnect. Orthogonally, we determine the semantics and interfaces needed by any hardware TM system to support rich software functionality in modern operating systems and programming languages. Finally, we extend hardware support for transactional execution to create a multi-core architecture that provides cache coherence and memory consistency at the granularity of atomic transactions. We conclude that programs written with transactional memory can achieve comparable to and often superior performance than the same programs written with traditional synchronization methods. Furthermore, a transactional architecture implementing lazy versioning and optimistic conflict detection is the preferred method of implementing TM in hardware due to its simplicity and good performance across a wide range of contention scenarios. Also, to support rich semantics, you need four mechanisms: two-phase transaction commit, software handlers, nested transactions, and non-transactional loads and stores. Finally, a continuously transactional architecture called Transactional Coherence and Consistency (TCC) maintains performance benefits while simplifying the hardware implementation of TM

Architectural semantics for practical transactional memory

Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional state buffering and conflict resolution. Missing is a robust hardware/software interface, not limited to simplistic instructions defining transaction boundaries. Without rich semantics, current TM systems cannot support basic features of modern programming languages and operating systems such as transparent library calls, conditional synchronization, system calls, I/O, and runtime exceptions. This paper presents a comprehensive instruction set architecture (ISA) for TM systems. Our proposal introduces three key mechanisms: two-phase commit; support for software handlers on commit, violation, and abort; and full support for open- and closed-nested transactions with independent rollback. These mechanisms provide a flexible interface to implement programming language and operating system functionality. We also show that these mechanisms are practical to implement at the ISA and microarchitecture level for various TM systems. Using an execution-driven simulation, we demonstrate both the functionality (e.g., I/O and conditional scheduling within transactions) and performance potential (2.2 × improvement for SPECjbb2000) of the proposed mechanisms. Overall, this paper establishes a rich and efficient interface to foster both hardware and software research on transactional memory.