Photonics and electronics integration in the HELIOS project

The objective of the European project HELIOS is to combine a photonic layer with a CMOS circuit by different innovative means, using microelectronics processes. Bonding of AWG + Ge Photodiodes on CMOS wafer is achieved

Wafer-Scale, Sub-5 nm Junction Formation by Monolayer Doping and Conventional Spike Annealing

We report the formation of sub-5 nm ultrashallow junctions in 4 inch Si wafers enabled by the molecular monolayer doping of phosphorous and boron atoms and the use of conventional spike annealing. The junctions are characterized by secondary ion mass spectrometry and non-contact sheet resistance measurements. It is found that the majority (~70%) of the incorporated dopants are electrically active, therefore, enabling a low sheet resistance for a given dopant areal dose. The wafer-scale uniformity is investigated and found to be limited by the temperature homogeneity of the spike anneal tool used in the experiments. Notably, minimal junction leakage currents (<1 uA/cm2) are observed which highlights the quality of the junctions formed by this process. The results clearly demonstrate the versatility and potency of the monolayer doping approach for enabling controlled, molecular-scale ultrashallow junction formation without introducing defects in the semiconductor.Comment: 21 pages, 5 figure

Schottky-Barrier height lowering by an increase of the substrate doping in PtSi Schottky barrier source/drain FETs

In this letter, the Schottky-barrier height (SBH) lowering in Pt silicide/n-Si junctions and its implications to Schottky-barrier source/drain p-field-effect transistors (p-SBFETs) are studied experimentally and numerically. We demonstrate that the increase of the n-Si substrate doping is responsible for a larger hole SBH lowering through an image-force mechanism, which leads to a substantial gain of the drive current in the long-channel bulk p-SBFETs. Numerical simulations. show that the channel doping concentration is also critical for short-channel p/n-silicon-on-insulator SBFET performance

Groups III and V impurity solubilities in silicon due to laser, flash, and solid-phase-epitaxial-regrowth anneals

In this work the authors studied impurity solubilities of groups III and V elements in silicon resulting from laser anneal, flash anneal, and solid-phase-epitaxial regrowth. Rutherford backscattering channeling analysis was used to determine substitutional impurity depth profiles generated from the difference between the random and aligned spectra. Despite the large difference in peak temperatures and times, the anneals produce similar results with maximum solubilities beating the maximum equilibrium values by one to two orders of magnitude depending on the impurity. The correlation between the metastable solubility and the equilibrium distribution coefficient allows a prediction of values for other impurities not extracted experimentally

Advanced GeOI structures: from material properties to high performance pMOSFETs.

International audienc

Advanced pMOSFET on germanium-on-insulator : low temperature properties.

National audienc

Germanium oxynitride (GeOxNy) as a back interface passivation layer for Germanium-on-insulator substrates

International audienc

Advanced pMOSFET on germanium-on-insulator : low temperature properties.

National audienc