Small Ultrasound-Based Corrosion Sensor for Intraday Corrosion Rate Estimation

The conventional way of studying corrosion in marine environments is by installing corrosion coupons. Instead, this paper presents an experimental field study using an unattended corrosion sensor developed on the basis of ultrasound (US) technology to assess the thickness loss caused by general atmospheric corrosion on land close to the sea (coastal region). The system described here uses FPGA, low-power microcontroller, analog front-end devices in the sensor node, and a Beaglebone black wireless board for posting data to a server. The overall system is small, operates at low power, and was deployed at Gran Canaria to detect the thickness loss of an S355 steel sample and consequently estimate the corrosion rate. This experiment aims to demonstrate the system's viability in marine environments and its potential to monitor corrosion in offshore wind turbines. In a day, the system takes four sets of measurements in 6 hour intervals, and each set consists of 5 consecutive measurements. Over the course of 5 months, the proposed experiment allowed for us to continuously monitor the corrosion rate in an equivalent corrosion process to an average thickness loss rate of 0.134 mm/year

Review of corrosion monitoring and prognostics in offshore wind turbine structures: current status and feasible approaches

As large wind farms are now often operating far from the shore, remote condition monitoring and condition prognostics become necessary to avoid excessive operation and maintenance costs while ensuring reliable operation. Corrosion, and in particular uniform corrosion, is a leading cause of failure for Offshore Wind Turbine (OWT) structures due to the harsh and highly corrosive environmental conditions in which they operate. This paper reviews the state-of-the-art in corrosion mechanism and models, corrosion monitoring and corrosion prognostics with a view on the applicability to OWT structures. Moreover, we discuss research challenges and open issues as well strategic directions for future research and development of cost-effective solutions for corrosion monitoring and prognostics for OWT structures. In particular, we point out the suitability of non-destructive autonomous corrosion monitoring systems based on ultrasound measurements, combined with hybrid prognosis methods based on Bayesian Filtering and corrosion empirical models

Ultrasound-Based Smart Corrosion Monitoring System for Offshore Wind Turbines

The ultrasound technique is a well-known non-destructive and efficient testing method for on-line corrosion monitoring. Wall thickness loss rate is the major parameter that defines the corrosion process in this approach. This paper presents a smart corrosion monitoring system for offshore wind turbines based on the ultrasound pulse-echo technique. The solution is first developed as an ultrasound testbed with the aim of upgrading it into a low-cost and low-power miniaturized system to be deployed inside offshore wind turbines. This paper discusses different important stages of the presented monitoring system as design methodology, the precision of the measurements, and system performance verification. The obtained results during the testing of a variety of samples show meaningful information about the thickness loss due to corrosion. Furthermore, the developed system allows us to measure the Time-of-Flight (ToF) with high precision on steel samples of different thicknesses and on coated steel samples using the offshore standard coating NORSOK 7A

Design of efficient viterbi decoders for communication transceivers. IEEE 802.11a case study.

Forward error correcting techniques have become fundamental tools to obtain robust and reliable communication networks. In this reward, convolutional coders belong to a family of codes used in applications such as deep space communications, LTE, GSM, UWB and WLAN. The Viterbi algorithm is a maximum likelihood decoder for convolutional codes. It operates recursively and in each iteration it discards the less probable messages that can have been transmitted. It is estimated that the Viterbi decoder is the most complex entity of the receiver chain of a multicarrier transceiver. In this research work the architecture of a flexible and parameterizable Viterbi decoder is presented. This flexibility allows us to quickly modify our architecture so that it decodes any given convolutional code. This way we can easily compare our implementation with other alternatives found in the literature. The decoder description does not make use of external or proprietary IPs, so the decoder can be easily ported to any FPGA manufacturer or ASIC technology. The Viterbi decoder is one of the most important building blocks of the receiver chain of a transceiver, and its performance is a clear indicator of the Bit Error Rate (BER) or Packet Error Rate (PER) we can expect from the system. The parametrization of our decoder implementation allows us to make trade offs between the complexity, area resource utilization, achievable clock speed and decoding capacity of the transceiver. However, making such a parametrical analysis, specially when the entire transceiver architecture is being analyzed under different channel configurations, is a time consuming task. In order to overcome this limitation, in this research work a fast Hardware in the Loop (HiL) evaluation platform has been designed. This platform allows us to quickly compare different decoder configurations and evaluate the performance of the transceiver architecture in which they are embedded. The HiL platform has proven to significantly reduce the simulation time of other alternatives such as RTL simulators. The case study of the parametrical analysis has been WLAN 802.11a. In this research work the sources of a WLAN 802.11a compliant transceiver have been obtained. The transceiver architecture is functional up to the MAC layer of the standard, and it includes complex components such as a time and offset synchronizer and equalizer and phase offset tracker. Also, during this research work a simple hardware oriented demapping algorithm has been proposed. By means of the HiL platform, the Viterbi decoder architecture has been optimized in terms of area resource utilization and its PER performance curves have been obtained for different transmission modes supported by the WLAN standard.Las técnicas de corrección de errores se han convertido en herramientas fundamentales para obtener redes de comunicación robustas y fiables. En este aspecto, los códigos convolucionales pertenecen a una familia de códigos usados en aplicaciones como comunicaciones de espacio profundo, LTE, GSM, UWB y WLAN. El algoritmo de Viterbi es un decodificador de máxima verosimilitud para códigos convolucionales. Opera de forma recursiva y en cada iteración descarta los mensajes que han sido transmitidos con menor probabilidad. Se ha estimado que el decodificador de Viterbi es la entidad de mayor complejidad en la cadena de recepción de un transceptor multiportadora. En este trabajo de investigación se presenta la arquitectura de un decodificador de Viterbi flexible y parametrizable. Esta flexibilidad permite modificar de forma rápida la arquitectura para poder decodificar cualquier código convolucional. De esta manera es posible comparar de forma rápida nuestra arquitectura con otras propuestas presentes en la literatura. La descripción del decodificador no hace uso de ninguna IP externa, por lo que el decodificador puede ser portado rápidamente a cualquier fabricante de FPGA o tecnología ASIC. El decodificador de Viterbi es uno de los bloques funcionales más importantes de la cadena de recepción de un transceptor, y su rendimiento es un claro indicador de las curvas de Tasa de Error de Bit (en inglés, Bit Error Rate o BER) o Tasa de Error de Paquete (en inglés, Packet Error Rate o PER) que podemos esperar del sistema. La parametrización de nuestro decodificador permite efectuar concesiones entre la complejidad, utilización de recursos de área, máxima velocidad de reloj y capacidad de decodificación del transceptor. Sin embargo, hacer un análisis paramétrico del transceptor, especialmente cuando éste debe ser analizado bajo distintas condiciones de canal, es una tarea que requiere mucho tiempo. Para superar esta limitación, en este trabajo de investigación se ha propuesto una plataforma rápida de verificación basada en Hardware-in-the-Loop (HiL). Esta plataforma permite comparar de forma rápida distintas configuraciones del decodificador y evaluar el rendimiento de la arquitectura del transceptor en la que se integra. La plataforma HiL ha demostrado reducir notablemente el tiempo de simulación comparada con alternativas como simulaciones RTL puras. El caso de estudio del análisis paramétrico ha sido WLAN 802.11a. Para este trabajo se han obtenido las fuentes de un transceptor compatible con el estándar WLAN 802.11a. La arquitectura del transceptor es funcional hasta la capa MAC del estándar, e incluye bloques de procesamiento complejos como un sincronizador de error de frecuencia y tiempo y un ecualizador de canal con seguimiento de fase. A lo largo de la realización de este trabajado de investigación también se ha propuesto un algoritmo sencillo de demapeo orientado a hardware. Por medio de la plataforma HiL la arquitectura del decodificador de Viterbi ha sido optimizada en términos de utilización de recursos hardware y se han obtenido las curvas de rendimiento PER para distintos modos de transmisión aceptados por el estándar WLAN

A Flexible Fog Computing Design for Low-Power Consumption and Low Latency Applications

In this paper, we propose a flexible Fog Computing architecture in which the main features are that it allows us to select among two different communication links (WiFi and LoRa) on the fly and offers a low-power solution, thanks to the applied power management strategies at hardware and firmware level. The proposed Fog Computing architecture is formed by sensor nodes and an Internet of Things (IoT) gateway. In the case of LoRa, we have the choice of implementing the LoRaWAN and Application servers on the cloud or on the IoT gateway, avoiding, in this case, to send data to the Cloud. Additionally, we have presented an specific setup and methodology with the aim of measuring the sensor node’s power consumption and making sure there is a fair comparison between the different alternatives among the two selected wireless communication links by varying the duty cycle, the size of the payload, and the Spreading Factor (SF). This research work is in the scope of the STARPORTS Interconnecta Project, where we have deployed two sensor nodes in the offshore platform of PLOCAN, which communicate with the IoT gateway located in the PLOCAN premises. In this case, we have used LoRa communications due to the required large distance between the IoT gateway and the nodes in the offshore platform (in the range of kilometers). This deployment demonstrates that the proposed solution operates in a real environment and that it is a low-power and robust approach since it is sending data to the IoT gateway during more than one year and it continues working

Small Ultrasound-Based Corrosion Sensor for Intraday Corrosion Rate Estimation

The conventional way of studying corrosion in marine environments is by installing corrosion coupons. Instead, this paper presents an experimental field study using an unattended corrosion sensor developed on the basis of ultrasound (US) technology to assess the thickness loss caused by general atmospheric corrosion on land close to the sea (coastal region). The system described here uses FPGA, low-power microcontroller, analog front-end devices in the sensor node, and a Beaglebone black wireless board for posting data to a server. The overall system is small, operates at low power, and was deployed at Gran Canaria to detect the thickness loss of an S355 steel sample and consequently estimate the corrosion rate. This experiment aims to demonstrate the system's viability in marine environments and its potential to monitor corrosion in offshore wind turbines. In a day, the system takes four sets of measurements in 6 hour intervals, and each set consists of 5 consecutive measurements. Over the course of 5 months, the proposed experiment allowed for us to continuously monitor the corrosion rate in an equivalent corrosion process to an average thickness loss rate of 0.134 mm/year

Design of efficient viterbi decoders for communication transceivers. IEEE 802.11a case study.

Forward error correcting techniques have become fundamental tools to obtain robust and reliable communication networks. In this reward, convolutional coders belong to a family of codes used in applications such as deep space communications, LTE, GSM, UWB and WLAN. The Viterbi algorithm is a maximum likelihood decoder for convolutional codes. It operates recursively and in each iteration it discards the less probable messages that can have been transmitted. It is estimated that the Viterbi decoder is the most complex entity of the receiver chain of a multicarrier transceiver. In this research work the architecture of a flexible and parameterizable Viterbi decoder is presented. This flexibility allows us to quickly modify our architecture so that it decodes any given convolutional code. This way we can easily compare our implementation with other alternatives found in the literature. The decoder description does not make use of external or proprietary IPs, so the decoder can be easily ported to any FPGA manufacturer or ASIC technology. The Viterbi decoder is one of the most important building blocks of the receiver chain of a transceiver, and its performance is a clear indicator of the Bit Error Rate (BER) or Packet Error Rate (PER) we can expect from the system. The parametrization of our decoder implementation allows us to make trade offs between the complexity, area resource utilization, achievable clock speed and decoding capacity of the transceiver. However, making such a parametrical analysis, specially when the entire transceiver architecture is being analyzed under different channel configurations, is a time consuming task. In order to overcome this limitation, in this research work a fast Hardware in the Loop (HiL) evaluation platform has been designed. This platform allows us to quickly compare different decoder configurations and evaluate the performance of the transceiver architecture in which they are embedded. The HiL platform has proven to significantly reduce the simulation time of other alternatives such as RTL simulators. The case study of the parametrical analysis has been WLAN 802.11a. In this research work the sources of a WLAN 802.11a compliant transceiver have been obtained. The transceiver architecture is functional up to the MAC layer of the standard, and it includes complex components such as a time and offset synchronizer and equalizer and phase offset tracker. Also, during this research work a simple hardware oriented demapping algorithm has been proposed. By means of the HiL platform, the Viterbi decoder architecture has been optimized in terms of area resource utilization and its PER performance curves have been obtained for different transmission modes supported by the WLAN standard.Las técnicas de corrección de errores se han convertido en herramientas fundamentales para obtener redes de comunicación robustas y fiables. En este aspecto, los códigos convolucionales pertenecen a una familia de códigos usados en aplicaciones como comunicaciones de espacio profundo, LTE, GSM, UWB y WLAN. El algoritmo de Viterbi es un decodificador de máxima verosimilitud para códigos convolucionales. Opera de forma recursiva y en cada iteración descarta los mensajes que han sido transmitidos con menor probabilidad. Se ha estimado que el decodificador de Viterbi es la entidad de mayor complejidad en la cadena de recepción de un transceptor multiportadora. En este trabajo de investigación se presenta la arquitectura de un decodificador de Viterbi flexible y parametrizable. Esta flexibilidad permite modificar de forma rápida la arquitectura para poder decodificar cualquier código convolucional. De esta manera es posible comparar de forma rápida nuestra arquitectura con otras propuestas presentes en la literatura. La descripción del decodificador no hace uso de ninguna IP externa, por lo que el decodificador puede ser portado rápidamente a cualquier fabricante de FPGA o tecnología ASIC. El decodificador de Viterbi es uno de los bloques funcionales más importantes de la cadena de recepción de un transceptor, y su rendimiento es un claro indicador de las curvas de Tasa de Error de Bit (en inglés, Bit Error Rate o BER) o Tasa de Error de Paquete (en inglés, Packet Error Rate o PER) que podemos esperar del sistema. La parametrización de nuestro decodificador permite efectuar concesiones entre la complejidad, utilización de recursos de área, máxima velocidad de reloj y capacidad de decodificación del transceptor. Sin embargo, hacer un análisis paramétrico del transceptor, especialmente cuando éste debe ser analizado bajo distintas condiciones de canal, es una tarea que requiere mucho tiempo. Para superar esta limitación, en este trabajo de investigación se ha propuesto una plataforma rápida de verificación basada en Hardware-in-the-Loop (HiL). Esta plataforma permite comparar de forma rápida distintas configuraciones del decodificador y evaluar el rendimiento de la arquitectura del transceptor en la que se integra. La plataforma HiL ha demostrado reducir notablemente el tiempo de simulación comparada con alternativas como simulaciones RTL puras. El caso de estudio del análisis paramétrico ha sido WLAN 802.11a. Para este trabajo se han obtenido las fuentes de un transceptor compatible con el estándar WLAN 802.11a. La arquitectura del transceptor es funcional hasta la capa MAC del estándar, e incluye bloques de procesamiento complejos como un sincronizador de error de frecuencia y tiempo y un ecualizador de canal con seguimiento de fase. A lo largo de la realización de este trabajado de investigación también se ha propuesto un algoritmo sencillo de demapeo orientado a hardware. Por medio de la plataforma HiL la arquitectura del decodificador de Viterbi ha sido optimizada en términos de utilización de recursos hardware y se han obtenido las curvas de rendimiento PER para distintos modos de transmisión aceptados por el estándar WLAN