Outil de CAO pour la génération d'opérateurs arithmétiques auto-contrôlables

ISBN 2-913329-70-5With the increasing integration density, new generations of integrated circuits are becoming more and more sensitive to noise sources such like power line disturbances, electromagnetic influence, etc.Further, it is now proved that some particles coming from the space (alpha particles and atmospheric neutrons) can also interfere deep sub-micron circuits operation (soft errors). Face to this challenge, self-checking techniques could provide good solutions. A good solution must of course result in reduced hardware overhead cost and little or no performance penalty. At that stage, two global difficulties appear. First, self-checking techniques are known by a restricted group of designers, and second, there are no professional CAD tools for automating self-checking circuits generation. In this work, we show that self-checking multipliers based on residue codes can result in a very little hardware overhead, especially for large multipliers. In a second time, we generalize fault secure solutions for multipliers, adders and shift registers based on the parity code. The new versions have several parity bits in order to increase fault coverage. We have implemented the presented solutions in a CAD tool developed by our research group. This tool offers many different self-checking arithmetic and logical operators to make flexible the construction of self-checking data paths.Le travail effectué dans cette thèse porte sur l'étude et la génération d'opérateurs arithmétiques auto-contrôlables. Cette thèse a été motivée par l'importance que prennent les techniques d'autocontrôle des circuits intégrés pour remédier aux problèmes de fiabilité qui sont majorés par la miniaturisation. Les chemins de données sont des parties logiques essentielles dans les microprocesseurs et les microcontrôleurs. La conception de chemins de données fiables est donc un pas important vers la réalisation de microprocesseurs plus sûrs. Dans un premier temps, nous avons étudié et implémenté des multiplieurs auto-contrôlables basés sur le code résidu. Nous avons montré qu'on peut avoir des multiplieurs sûrs en présence de fautes de type collage logique avec un surcoût très faible, notamment dans le cas des multiplieurs de grandes tailles (de 10 à 15% pour les multiplieurs de taille 32x32). Dans un deuxième temps, nous avons généralisé des solutions auto-contrôlables existantes d'opérateurs arithmétiques basés sur la parité. Les nouvelles versions ont plusieurs bits de parité et permettent d'augmenter sensiblement la couverture de fautes dans le cas des fautes transitoires. Les solutions développées sont toutes intégrées dans un outil informatique

A CAD framework for generating self-checking multipliers based on residue codes

ISBN: 0769500781The basic drawbacks related to the design of self-checking circuits include high hardware cost and design effort. Recent developments on self-checking operators based on parity prediction compatible schemes allow us to achieve high fault coverage and low hardware cost in self-checking data paths for the majority of basic data path blocks such as, adders, ALUs, shifters, register files, etc. However, parity prediction self-checking multipliers involve hardware overhead significantly higher than for other blocks. Thus, large multipliers will increase significantly the hardware overhead of the whole data path. Residue arithmetic codes allow to reduce this cost The tools presented in this paper generate automatically self-checking multipliers using such codes. They complete our tools using parity prediction for various other blocks, and enable automatic generation of low cost self-checking data paths

A CAD Framework for Generating Self-Checking Multipliers Using Residue Arithmetic Codes

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Self-checking circuits versus realistic faults in very deep submicron

ISBN: 0769506135IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise as well as to small manufacturing defects that may result in spurious faults. Such faults are difficult to (or can not) be detected by manufacturing testing and will result in unacceptable rates of errors in the field. Self-checking design can be used to cope with this problem, but usually it addresses logic faults. This paper analyzes the behavior of self-checking circuits under various spurious faults likely to occur in very deep submicron technologies

A CAD framework for efficient self-checking data path design

International audienceThe basic drawbacks related to the design of self-checking circuits include high hardware cost and high design efforts. Recent developments on self-checking operators based on parity prediction compatible schemes allow us to achieve high fault coverage and low hardware costs. The integration of these schemes in a dedicated CAD tool allows automatic generation, thus it reduces design efforts and makes self-checking circuits very attractive

Damage in crystalline silicon by swift heavy ion irradiation

We have studied damage of crystalline Si surfaces induced by electronic energy loss of swift heavy ions with an electronic stopping power of up to S e = 12 keV/nm. Scanning tunneling microscope images of the surface after irradiation under perpendicular as well as glancing angles of incidence showed no surface damage. We have performed theoretical calculations for the damage threshold within the two temperature model, resulting in View the MathML sourceSeth=8 keV/nm as the minimum stopping power to create a molten zone. We investigate the respective influence of the electron–phonon coupling, of the criterion at which the damage occurs and a possible effect of ballistic electrons. We show that the latter has the strongest effect on the calculated damage threshol

Surface structure modification of single crystal graphite after slow, highly charged ion irradiation

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Electronic sputtering: angular distributions of (LiF)

A combination of imaging techniques (XY) and time-of-flight (TOF) spectroscopy was used to measure the complete velocity vector of sputtered positive secondary ions in collisions of Kr33+ (10.1 MeV/u) with well prepared LiF single crystals in the electronic stopping regime. The angular distributions of (LiF)nLi+ clusters become broader with increasing cluster size n. This could be an indication of contributions from different ejection mechanisms. The experimental secondary ion angular distributions can be fitted by a simple cosine function of the type N(θ) = A cosm(θ), but it does not reproduce the shape of the jet-like structure observed for the emission of neutral LiF particles perpendicular to the ion beam. Therefore, the cluster emission hypothesis does not explain in a simple way the observed narrow jet