Design of a high speed and low latency crypto-processor ASIC

This paper presents the design of an ultra high speed crypto-processor for next generation IT security. It addresses the next generation IT security requirements: the resistance against all attacks and high speed with low latency. The proposed processor is capable of generating cryptographically secured information at a rate of multi-ten Gbps. The performance of the processor is compared with that of other researchers which proves it's superiority over them

Radiation measurement from mobile base stations at a university campus in Malaysia

The tremendous growth of telecommunication industry results the number of hand phone users increases everyday. In order to support the growing number of users, the mobile base stations can be seen in almost everywhere. This scenario has created uncomfortable feelings to the people that they may be affected by the radiations from antennas. A measurement was done at student hostels and office premises near to base stations in International Islamic University Malaysia, Gombak campus. Measured values are compared with Malaysian Communication and Multimedia Commission (MCMC), IEEE and ANSI recommendations for safety guidelines. The results are presented in this study

RC4A stream cipher for WLAN security: a hardware approach

Wireless networks are on the cutting edge of modern technology and rapidly gaining popularity in today’s world due to their excellent usability. For secure wireless data transmission, Wired Equivalent Privacy (WEP), IEEE 802.11 standard defined security protocol, is employed. WEP has a potential limitation that stems from its adaptation of RC4 stream cipher algorithm. As a result, there is a pressing need for new WLAN security measure. Therefore, this paper presents hardware implementation of RC4A stream cipher and proposes to replace RC4 in WLAN security scheme, due to weakness of RC4.The design of the cipher was implemented by Verilog HDL. For hardware implementation of the design, an Altera Field Programmable Gate Array (FPGA) device, EP20K200EFC484-2X from APEX family, APEX 20KE, was used

Discovering decision algorithm from a distance relay event report

In this study rough-set-based data mining strategy was formulated to discover distance relay decision algorithm from its resident event report. This derived algorithm, aptly known as relay CD-prediction rules, can later be used as a knowledge base in support of a protection system analysis expert system to predict, validate or even diagnose future unknown relay events. Nowadays protection engineers are suffering from very complex implementations of protection system analysis due to massive quantities of data coming from diverse points of intelligent electronic devices. In helping the protection engineers deal with this overwhelming data, this study relied merely on digital protective relay’s recorded event report because, among other intelligent electronic devices, digital protective relay sufficiently provided virtually most attributes needed for data mining process in knowledge discovery in database. The method of discovering the distance relay decision algorithm essentially involved formulating rough set discernibility matrix and function from relay event report, finding reducts of pertinent attributes using genetic algorithm and finally generating relay prediction rules. The classification accuracy and the area under the ROC curve measurements provided an acceptable evaluation of the fact that the discovered relay decision algorithm

Knowledge discovery in distance relay event report: a comparative data-mining strategy of rough set theory with decision tree

A protective relay performance analysis is only feasible when the hypothesis of expected relay operation characteristics as decision rules is established as the knowledge base. This has been meticulously accomplished by soliciting the relay knowledge domain from protection experts who are usually constrained by their experience and expertise. Manually analyzing an event report is also cumbersome due to the tremendous amount of data to be perused. This paper addresses these issues by intelligently divulging the knowledge hidden in the relay recorded event report using a data-mining strategy based on rough set theory and a rule-quality measure under supervised learning to discover the relay decision algorithm and association rule. The high prediction accuracy rate and the close-to-unity areas under ROC curve value of the relay operating characteristic curve of the discovered relay decision algorithm verifies its generalized ability to predict trip status in an expert system of relay performance analysis. The relay association rule that was subsequently discovered by using the rule-quality analysis had also been verified as being a reliable hypothesis of the relay operation characteristics. This hypothesis helps the protection engineers understand the behavior of the distance relay. These rules would then be compared with and validated by benchmarking decision-tree-based data-mining analysis

Development of a Functional Digital Integrated Circuit Testing System Using Mixed-Mode Technique

With the continuous increase in design complexities and packing densities of integrated circuit (IC), problems associated with conventional Automatic Test Equipment (ATE)-based IC testing approach have become a burning issue in the semiconductor world, which needs an economic solution with reliable performance. Recently, the superiority of Dynamic Reseeding-based Mixed-mode (DRM) technique has been proven over all other existing test techniques in the Built-in Self-Test (BIST) environment. This thesis introduces the implementation of the DRM technique in a system-on-a-chip (SOC) in alleviating the problems of conventional ATE-based external testing of digital IC. The performance of the SOC in IC testing has been verified using fault simulation experiments on the ISCAS85 benchmark circuits (Circuits proposed in the International Symposium on Circuits and Systems in 1985). Significant improvement is observed in achieving complete fault coverage for the ISCAS85 benchmark circuits using acceptable number of test vectors. Fault simulation results show that the proposed DRM technique produces 100% fault coverage for the benchmark circuits c432, c1355, c1908, c2670, c3540 and c5315 using the 232, 526, 996, 336, 360 and 748 test cubes, respectively which are much lower than the numbers from the approaches suggested by other researchers. It also offers much lower data storage requirements in IC testing than the conventional ATE-based testing approach. The results show that 2 to 11 times less memory is needed for testing the ISCAS85 benchmark circuits using the DRM technique than that of the deterministic testing approach. Verilog Hardware Description Language (HDL), which is an industry standard IC design tool, has been used to design the SOC proposed in this thesis. Main modules of the SOC are micro-UART (Universal Asynchronous Receiver and Transmitter), a controller, pattern generator, signature analyzer (SA), instruction registers and Random Access Memories (RAMs). A prototype test set-up has been developed for testing IC by implementing the design of the SOC into a Field Programmable Gate Array Logic (FPGA) chip and then by interfacing the FPGA chip with a personal computer (PC) through a Graphical User Interface (GUI). For testing a circuit, necessary test information is loaded into the SOC and the testing process is executed using the GUI from the PC. The SOC goes into autonomous mode. It generates test vectors, applies them to the Circuit Under Test (CUT) and captures the output responses and sends it into the SA for compression. At the end of testing, the generated signature is compared with that of a reference circuit (fault-free circuit of the same type) and the CUT is identified as fault-free if the two signatures are the same and as faulty if otherwise. The operation of the SOC has been verified in real time by testing a 16-bit multiplier as a sample CUT. It is user programmable, which increases flexibility and reliability in IC testing. It is capable of testing functionality of combinational circuits as well as sequential circuits with scan-path facility

Diagnosis of heart diseases: A fuzzy-logic-based approach.

Cardiovascular diseases (CVD) also known as heart disease are now the leading cause of death in the world. This paper presents research for the design and creation of a fuzzy logic-based expert system for the prognosis and diagnosis of heart disease that is precise, economical, and effective. This system entails a fuzzification module, knowledge base, inference engine, and defuzzification module where seven attributes such as chest pain type, HbA1c (Haemoglobin A1c), HDL (high-density lipoprotein), LDL (low-density lipoprotein), heart rate, age, and blood pressure are considered as input to the system. With the aid of the available literature and extensive consultation with medical experts in this field, an enriched knowledge database has been created with a sufficient number of IF-THEN rules for the diagnosis of heart disease. The inference engine then activates the appropriate IF-THEN rule from the knowledge base and determines the output value using the appropriate defuzzification technique after the fuzzification module fuzzifies each input depending on the appropriate membership function. Moreover, the fusion of web-based technology makes it suitable and cost-effective for the prognosis of heart disease for a patient and then he can take his decision for addressing the problem based on the status of his heart. On the other hand, it can also assist a medical practitioner to reach a more accurate conclusion regarding the treatment of heart disease for a patient. The Mamdani inference method has been used to evaluate the results. The system is tested with the Cleveland dataset and cross-checked with the in-field dataset. Compared with the other existing expert systems, the proposed method performs 98.08% accurately and can make accurate decisions for diagnosing heart diseases

Delay, Power and Area Estimation of the Proposed Designs.

<p>Delay, Power and Area Estimation of the Proposed Designs.</p

Optimized pipelined architecture for byte substitution.

<p>Optimized pipelined architecture for byte substitution.</p

Area (GE) versus target value for critical path delay (ns).

<p>Area (GE) versus target value for critical path delay (ns).</p